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Technical
Seminar |
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A 65nm Dual-Core
Multi-Threaded Xeon® Processor with 16MB L3 Cache |
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DATE/TIME
Monday, April 10, 2006
(4:30pm to 5:30pm)
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PLACE
Bldg. 1 Auditorium (Avago
Technologies, Fort Collins, CO, formerly Agilent Technologies) |
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DIRECTIONS
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Non-Avago
Attendees: Please arrive punctually at 4:15pm as you will
need to be escorted to the seminar
room. RSVP to
bob.barnes@avagotech.com
to expedite sign-in and to help us with a headcount estimate for
food/drinks. |
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From I-25, take Harmony Road Exit (Exit
265) westbound, and enter Agilent/HP campus on right. Avago/HP/Intel
campus is on the NE corner of Harmony Road and Ziegler Road.
Proceed to Bldg. 1 Lobby to sign-in and meet host for escort to
Auditorium. |
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COST
Free. As always, food &
drinks will be provided. |
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ABSTRACT
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This talk describes the
next-generation dual-core 64-bit Xeon® MP processor
implemented in a 65nm 8M process. The 435mm2 die has 1.328B
transistors. Each core has two threads and a unified 1MB L2 cache.
The 16MB unified, 16-way set-associative L3 cache implements both sleep
and shut-off leakage reduction modes. The clock distribution
achieves 11ps global clock skew. A sparse clock grid is implemented over
the cache to save power. Extensive use of long channel devices reduces
leakage in non-timing critical paths. |
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PRESENTATION SLIDES
pdf
ISSCC paper
(copyright by IEEE) |
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STEFAN
RUSU (Intel Corporation, Santa Clara, CA)
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Stefan Rusu (M’85-SM’01) received the MSEE
degree from the Polytechnic Institute in Bucharest, Romania. He
first joined Intel Corp. in 1984 working on data communications
integrated circuits. In 1988, he joined Sun Microsystems working
on microprocessor design with focus on clock and power distribution,
packaging, standard cell libraries, CAD and circuit design methodology.
He re-joined Intel Corp. in 1996 working on the clock and power
distribution, cell library, I/O buffers and package for the first
Itanium® processor. He is
presently a Senior Principal Engineer in Intel's Enterprise
Microprocessor Group leading the technology and special circuits design
team for the Xeon® Processors Family. His technical
interests are high-speed clocking, power distribution, I/O buffers,
power and leakage reduction, and high-speed circuit design techniques. |
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Stefan has authored or co-authored more than
70 papers on VLSI design methodology and microprocessor circuit
technology. He holds 25 U.S. patents with several more pending.
He is a member of the Technical Program Committee for ESSCIRC, A-SSCC and SoC conferences and
an Associate Editor of the IEEE Journal of Solid-State Circuits. |
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