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	Technical Seminar Distinguished Lecturer Series


	Ultra-low Voltage Nanoscale Embedded RAMs

	DATE/TIME Thursday, June 15, 2006 (4:30pm to 6:00pm)
	PLACE Bldg. 1 Auditorium (Avago Technologies, Fort Collins, CO, formerly Agilent Technologies)
	DIRECTIONS
	Non-Avago Attendees: Please arrive punctually at 4:15pm as you will need to be escorted to the seminar room. RSVP to bob.barnes@avagotech.com to expedite sign-in and to help us with a headcount estimate for food/drinks.
	From I-25, take Harmony Road Exit (Exit 265) westbound, and enter Agilent/HP campus on right. Avago/HP/Intel campus is on the NE corner of Harmony Road and Ziegler Road. Proceed to Bldg. 1 Lobby to sign-in and meet host for escort to Auditorium.
	COST Free. As always, food & drinks will be provided.

	ABSTRACT
	RAM cells and peripheral logic circuits of low-voltage nano-scale embedded RAMs are described. In particular, essential differences between the one-transistor one-capacitor (1-T) DRAM cell and the six-transistor (6-T) SRAM cell are clarified in terms of low-voltage operation. In addition, state-of-the-art circuits and devices to reduce subthreshold currents and variations in speed and leakage caused by PVT (process, voltage, and temperature) variations are described in detail.
	In this talk, first, general trends in low-voltage RAMs are explained. Second, challenges to low-voltage RAM cells and peripheral logic circuits are clarified. Third, RAM cell issues are discussed. Here, the low-voltage limitation of the 1-T and 6-T cells is investigated in terms of signal charge, signal voltage, noise, and cell size. Suppression of the ever-increasing threshold-voltage (V_T) variation with device scaling, which seriously degrades the sense margin of the 1-T cell and the voltage margin of the 6-T cell, the ECC circuit to cope with the ever-increasing soft-error rate and V_T variation, and power-supply controls of the 6-T cell are also explained. Fourth, peripheral circuits are discussed with respect to leakage reduction and compensation for speed variations caused by V_T variations. Fully-depleted-SOI devices and circuits to reduce the variations are also explained. Finally, two approaches are envisioned, which are high-V_DDbulk-CMOS for low-cost RAMs and low-V_DDFD-SOI for high-speed low-power RAMs.
	PRESENTATION SLIDES pdf
	REFERENCE
	Paper from IEEE International Symposium on Circuits and Systems (ISCAS-2006)

	DR. KIYOO ITOH (Hitachi Central Research Laboratory, Tokyo, Japan)
		Kiyoo Itoh received the BS and PhD degrees in electrical engineering from Tohoku University, Sendai, Japan, in 1963 and 1976 respectively. He is currently a Hitachi Fellow. He was a Visiting MacKay Lecturer at U.C. Berkeley in 1994, a Visiting Professor at the University of Waterloo in 1995, and a Consulting Professor at Stanford University in 2000-2001. He was a Member of the IEEE Fellow Committee from1999 to 2002, and an elected AdCom Member of IEEE Solid-State Circuits Society from 2001 to 2003. He is a Distinguished Lecturer of the IEEE Solid-state Circuits Society. Since 1972, he has led RAM circuit technology at Hitachi Ltd, being lead designer of the first prototype for eight generations of Hitachi DRAMs ranging from 4kb to 64Mb. As early as 1988, he pioneered circuit inventions and developments to reduce subthreshold current of MOSFETs even for the active mode, which is highlighted today in low-voltage CMOS LSI design.
	He holds over 370 patents in Japan and US. He authored three books and three book chapters on memory designs, and contributed over 130 technical papers and presentations, many of them invited, in IEEE journals and conference proceedings.
	Dr. Itoh has won many honors. They include the IEEE Paul Rappaport Award in1984, the Best Paper Award of ESSCIRC90, the 1993 IEEE Solid-State Circuits Award, and the 2006 IEEE Jun-ichi Nishizawa Medal. He is an IEEE Fellow. In Japan, his awards include the National Invention Award in 1989, the Commendation by the Minister of State for Science and Technology in 1997, and the National Medal of Honor with Purple Ribbon in 2000.