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Technical
Seminar
Distinguished Lecturer Series |
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60-GHz RF Transceivers in CMOS: Why and How? |
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DATE/TIME
Tuesday, August 1, 2006
(5:30pm to 7:00pm) |
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PLACE
Bldg. 1 Auditorium (Avago
Technologies, Fort Collins, CO, formerly Agilent Technologies) |
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DIRECTIONS
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Non-Avago
Attendees: Please arrive punctually at 5:15pm as you will
need to be escorted to the seminar
room. RSVP to
bob.barnes@avagotech.com
to expedite sign-in and to help us with a headcount estimate for
food/drinks. |
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From I-25, take Harmony Road Exit (Exit
265) westbound, and enter Agilent/HP campus on right. Avago/HP/Intel
campus is on the NE corner of Harmony Road and Ziegler Road.
Proceed to Bldg. 1 Lobby to sign-in and meet host for escort to
Auditorium. |
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COST
Free. As always, food &
drinks will be provided. |
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ABSTRACT
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The 7-GHz unlicensed band around 60 GHz offers
the possibility of wireless communication at data rates reaching several
gigabits per second. Moreover, the short wavelength allows
integration of the antenna on-chip and opens prospects for beamforming and
MIMO signaling. |
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With multiple antennas and transceivers
operating on one chip, and with the enormous analog
and digital signal processing required for high-rate communications, the
use of CMOS technology becomes attractive and perhaps essential. |
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This seminar presents the challenges in
circuit and architecture design for 60-GHz CMOS transceivers and
summarizes recent work on such critical building blocks as receiver front
ends, transmitter front ends, and frequency dividers. |
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PRESENTATION SLIDES
pdf |
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PROF. BEHZAD
RAZAVI (University of California, Los Angeles, CA)
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Behzad Razavi received the BSEE degree from
Sharif University of Technology in 1985 and the MSEE and PhDEE degrees
from Stanford University in 1988 and 1992, respectively. He was with
AT&T Bell Laboratories and Hewlett-Packard Laboratories until 1996.
Since 1996, he has been Associate Professor and subsequently Professor
of electrical engineering at University of California, Los Angeles. His
current research includes wireless transceivers, frequency synthesizers,
phase-locking and clock recovery for high-speed data communications, and
data converters. |
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Professor Razavi was an Adjunct
Professor at Princeton University from 1992 to 1994, and at Stanford
University in 1995. He served on the Technical Program Committees of the
International Solid-State Circuits Conference (ISSCC) from 1993 to 2002
and VLSI Circuits Symposium from 1998 to 2002. He has also served as
Guest Editor and Associate Editor of the IEEE Journal of Solid-State
Circuits, IEEE Transactions on Circuits and Systems, and International
Journal of High Speed Electronics. |
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Professor Razavi was also recognized as one
of the top 10 authors in the 50-year history of ISSCC. He is an IEEE
Distinguished Lecturer, a Fellow of IEEE, and the author of Principles
of Data Conversion System Design (IEEE Press, 1995), RF Microelectronics
(Prentice Hall, 1998) (translated in Chinese and Japanese), Design of
Analog CMOS Integrated Circuits (McGraw-Hill, 2001) (translated in
Chinese and Japanese), and Design of Integrated Circuits for Optical
Communications (McGraw-Hill, 2003). He was the editor of Monolithic
Phase-Locked Loops and Clock Recovery Circuits (IEEE Press, 1996), and
Phase-Locking in High-Performance Systems (IEEE Press, 2003). |
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Website |
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PHOTOS
Courtesy of Tin Tin Wee |
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