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Technical Seminar

From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD campus on right immediately following Harmony/Ziegler intersection.  AMD is located on the NW corner of Harmony Road and Ziegler Road.  Proceed to 3rd floor for escort to seminar auditorium.  Non-AMD employees:  please arrive at 4:15pm for security sign-in and escort.

Processor designers and the VLSI industry in general have truly hit the power wall.  Many options have been and are being explored to mitigate or circumvent the impact of power limits on performance, but all of these solutions have limited effect and application.  The implications of this fundamental limit are far reaching for processor architectures and the shape of computing in coming years.  This paper explores the nature of power limitations and some of the implications for the future of processor design.

Sam Naffziger received the BSEE degree from the California Institute of Technology, Pasadena, CA, in 1988, and the MSEE degree from Stanford University, Stanford, CA, in 1993.  He joined Hewlett Packard in 1988, and spent eight years working on various aspects of the PA-RISC processor development including floating point out-of-order execution and circuit methodologies.  He then became part of the Itanium2 Joint Development Team with Intel Corporation, Fort Collins, CO, and has led the design of both the first Itanium2 processor, and most recently, the Montecito design.  In 2006, he joined the Mile High Design Center of Advanced Micro Devices in Fort Collins, CO, working on next generation processor designs.  He holds 62 U.S. patents on processor circuits and architecture and has over 20 IEEE publications and presentations.  Mr. Naffziger chairs the International Solid-State Circuits Conference Digital Subcommittee, and is an AMD Senior Fellow.