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Technical
Seminar
Distinguished Lecturer Series |
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Taming the Beast -- Practical Tips for Phase-Locked Loop
Design |
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DATE/TIME
May 31, 2007 (5:00pm to 6:30pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter
AMD campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW
corner of Harmony Road and Ziegler Road. Proceed to 3rd floor for
escort to seminar auditorium. Non-AMD
employees: please arrive at 4:45pm for security sign-in and escort. |
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT
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The literal heartbeat of many VLSI designs,
the phase-locked loop (PLL) is an often feared and misunderstood beast.
Black-box designs from IP vendors are integrated on-chip with little
understanding of the PLL's sensitivities to process and digital noise.
Inexperienced designers read the latest literature and try to hit a
"home run" with their first PLL. Ignorance of the PLL's internal
workings leads to impossible-to-meet specs and inadequate test features.
This presentation provides a practical introduction to PLL design for
clock generation and high-speed IO, including feedback stability, common
circuit implementations, measurement techniques, and design for test.
Examples of PLL "gotchas" and real-world failures abound. |
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PRESENTATION SLIDES
pdf |
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DENNIS
FISCHETTE (AMD, Sunnyvale, CA)
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Dennis Fischette is a Senior Member of the
Technical Staff at Advanced Micro Devices (AMD) in Sunnyvale, CA.
In 1986 he graduated from Cornell University, Ithaca, NY, with BS
degree in Engineering Physics and then studied the History of Science at
the University of California, Berkeley. From 1988 to 1991, he
worked for Integrated CMOS Systems (Sunnyvale) on device and circuit
modeling. From 1991 to 1996, he worked for Hal Computer Systems (Campbell,CA)
on clock synthesizers and circuit design automation. Before
joining AMD, he worked for Chromatic Research (Sunnyvale) on clock
synthesizers, D/A circuits, and memories. His technical interests
include PLL and DLL design, clock-and-data recovery, circuit analysis
software, and high-speed IO circuits. He was a member of the ISSCC
Digital Program Committee from 2001-2006 and created an online course on
PLL Design for the IEEE Xplore program in 2005. In his spare time,
Dennis is an active jazz musician who recently performed in China and
Vietnam |
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Website |
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PHOTOS Courtesy of Tin Tin Wee |
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