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Technical
Seminar
Distinguished Lecturer Series |
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Bandwidth Extension Techniques in CMOS for Wireline/Wireless
Communications |
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DATE/TIME
Thursday, August 30, 2007 (4:30pm to 6:00pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 4:15pm for security sign-in and escort. |
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT |
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Circuit
design for digital links and optical transceivers involves three
critical challenges: wide bandwidth (BW), high gain and low power.
Conventional approaches trade off wide BW for low gain because the
gain-BW product increases as gain decreases; multiple-stage cascades
trade off high gain for power, area and BW shrinkage. Peaking techniques
for single-stage amplifiers achieve high gain simultaneously with high
BW extension ratios (BWER), which means fewer stages. Increases in BWER
and gain are achieved using capacitor-splitting and
magnetic-coupling to sequence charging currents in bridged-shunt
series and asymmetric T-coil amplifiers. |
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UWB
communication systems use a 3.1-10.6GHz spectrum. LNA design is critical
in a UWB receiver; it should exhibit low return loss, low noise figure,
high gain across 7.5GHz, and consume minimum power and die area. Cost
and SoC considerations dictate the use of CMOS. Previous designs use
common-source or distributed amplifiers; good performance is achieved,
but reductions in power and die area are desired. A common-gate UWB LNA
is described with low power and an area efficient impedance match along
with stagger-compensated series peaking for BW extension. |
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PRESENTATION SLIDES
pdf |
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REFERENCES |
- S. Shekhar et al., "Bandwidth
Extension Techniques for CMOS Amplifiers," IEEE J. Solid-State
Circuits, vol. 41, no. 11, Nov. 2006 (copyright by IEEE)
- X. Li et al., "Gm-Boosted
Common-Gate LNA and Differential Colpitts VCO/QVCO in 0.18-um CMOS,"
IEEE J. Solid-State Circuits, vol. 40, no. 12, Dec. 2005
(copyright by IEEE)
- X. Li et al., "Low-Power
gm-boosted LNA and VCO Circuits in 0.18um CMOS," ISSCC 2005
(copyright by IEEE)
- S. Galal and B. Razavi, "40-Gb/s
Amplifier and ESD Protection Circuit in 0.18-um CMOS Technology,"
IEEE J. Solid-State Circuits, vol. 39, no. 12, Dec. 2004 (copyright
by IEEE)
- B. Analui and A. Hajimiri, "Bandwidth
Enhancement for Transimpedance Amplifiers," IEEE J. Solid-State
Circuits, vol. 39, no. 8, Aug. 2004 (copyright by IEEE)
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PROF.
DAVID J. ALLSTOT (University of
Washington, Seattle, WA)
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David J. Allstot
received the B.S. from Univ. of Portland, M.S. from Oregon State Univ.,
and Ph.D. from Univ. of California, Berkeley. He has held several
industrial and academic positions, and has been at the Univ. of
Washington since 1999 where he is the Boeing-Egtvedt Chair Professor of
Engineering; he previously served as Chair of the Dept. of Electrical
Engineering. Dr. Allstot has advised almost 100 M.S. and Ph.D.
graduates and published about 275 papers. Awards include: IEEE Baker
Award, IEEE Circuits and Systems Society Darlington Award, IEEE Intl.
Solid-State Circuits Conference B. Winner Award, Technical Achievement
Award, IEEE Circuits and Systems Society, and Aristotle Award,
Semiconductor Research Corporation. He has performed service with
the IEEE Circuits and Systems Society and the IEEE Solid-State Circuits
Society. Prof. Allstot is an IEEE Fellow. |
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Website |
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PHOTOS Courtesy of Tin Tin Wee |
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