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Technical
Seminar |
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An Integrated Quad-Core Opteronä Microprocessor
(Greyhound /Deerhound) |
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DATE/TIME
Thursday, August 2, 2007 (4:30pm to 5:30pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take
Harmony Road Exit (Exit 265) westbound, AMD is a few miles west of the
exit, located on the NW corner of Harmony Road and Ziegler Road.
Through mid-August, the Harmony/Ziegler intersection is under heavy road
construction, and you must enter the AMD campus from the Ziegler
entrance, just north of Harmony.
Detour: After exiting I-25 (Exit 265),
watch for detour signs on the right, which will prompt cars to turn
north onto a dirt road called Strauss Cabin Road. This road will bend
around onto Horsetooth Road. Once you reach the intersection of
Horsetooth and Ziegler (stop sign),turn left (through the road
construction signs that allow local traffic only). Drive south on
Ziegler until and turn right onto AMD campus before reaching Harmony
intersection.
Proceed to 3rd floor for
escort to seminar auditorium. Non-AMD
employees: please arrive at 4:15pm for security sign-in and escort.
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT
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This talk presents the next generation AMD
Opteron processor that integrates 4-enhanced performance x86 cores
(quad-core) each with 512kB L2 cache and an enhanced 128-bit FPU.
The cores are integrated with a shared 2MB L3 cache and an enhanced
on-chip memory controller that supports up to four 16-bit HyperTransport
links and a dual-channel 128-bit DDR2/DDR3 interface. The design
contains over 450 million transistors fabricated in a 65nm
silicon-on-insulator (SOI) CMOS process with dual stress liners and
embedded SiGe for PMOS source/drains. The design utilizes
11-layers of copper interconnect that include advanced low-K
dielectrics. The SoC chip was designed to facilitate maximum reuse
of functional components and to provide flexibility to create targeted
variations. The talk will discuss various circuits used to implement
this Microprocessor as well as highlighting some of the design
challenges and how they were overcome. |
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PRESENTATION SLIDES
pdf |
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REFERENCE |
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DR. SHAWN
SEARLES (AMD, Austin, TX)
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Shawn Searles received his BScEE from
the University of Manitoba in 1987, MEng from Carleton University in
1989 and his PhD from the University of British Columbia in 1995.
From 1987 to 1992, he worked at Bell Northern Research on SONET systems
and at Northern Telecom on compact transistor models. From 1995 to
2001, Shawn worked at Intel Corp. on Pentium II, III and IV
microprocessors. From 2001 to 2003, Shawn worked at Accelerant
Networks on PAM-4 and PAM-2 SerDes that achieved data rates between
5Gb/s and 12Gb/s per lane. Since 2003, Dr. Searles has been a
Fellow at Advanced Micro Devices (AMD) working on K8 microprocessor
designs. His areas of interest include physical layer hardware
design, dynamic circuit design, register-file and cache designs,
mixed-signal circuits, statistical analysis methods for modeling
within-die variation and modeling of non-linear phenomena. |
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PHOTOS Courtesy of Tin Tin Wee |
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