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Technical
Seminar |
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Joint Architecture and Circuit Techniques to Address
Process and Voltage Variability |
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DATE/TIME
Thursday, November 1, 2007 (4:30pm to 6:30pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take
Harmony Road Exit (Exit 265) westbound, AMD is a few miles west of the
exit, located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for
escort to seminar auditorium. Non-AMD
employees: please arrive at 4:15pm for security sign-in and escort.
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT
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Technology scaling has enabled
tremendous growth in the IC industry over the past few decades.
While Moore's Law seems to be going strong, fine line widths in current
and future
nanoscale technologies (e.g., 45nm and below) present several obstacles
that have the potential to limit continued device scaling, curtail
frequency improvements, and cause increased leakage power in future
microprocessors. Faced with these challenges, software,
architecture and circuits researchers at Harvard have joined forces to
find holistic solutions in a collaborative fashion. |
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This talk will focus on
two such efforts. First, we discuss the challenges and
system-level advantages of replacing traditional 6T SRAM cells with
dynamic memories within latency-sensitive structures such as register
files and L1 caches. Second, we investigate the feasibility of
building integrated on-chip voltage regulators that enables nanosecond
scale voltage transitions for fast dynamic voltage and frequency scaling
(DVFS) to reduce power. These research efforts seek to provide
effective solutions to process and voltage variability problems by
leveraging tradeoffs across traditional research boundaries, potentially
yielding much higher payoffs compared to localized optimizations and
patches. |
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PRESENTATION SLIDES
pdf |
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PROF.
GU-YEON WEI (Harvard University, Cambridge, MA) |
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Gu-Yeon Wei joined Harvard University in
January 2002 and is currently an Associate Professor of Electrical
Engineering. Prior to joining Harvard, he spent 18 months at
Accelerant Networks in Beaverton, OR as a Senior Design Engineer.
Prof. Wei received his BS, MS, and Ph.D. degrees all from Stanford
University in 1994, 1997, and 2001. His current research interests
are in the area of mixed-signal VLSI circuits and systems design for
high-speed/low-power wireline data communication, low-jitter clock
generation, energy-efficient computing devices for sensor networks, and
collaborative architecture + circuit techniques to overcome variability
in nanoscale IC technologies. |
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Website |
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PROF.
DAVID BROOKS (Harvard University, Cambridge, MA) |
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David Brooks joined Harvard University in
September of 2002 and is currently an Associate Professor of Computer
Science. Dr. Brooks received his BS (1997) degree from the
University of Southern California and his MA (1999) and PhD (2001)
degrees from Princeton University, all in Electrical Engineering.
Prior to joining Harvard University, Dr. Brooks was a Research Staff
Member at IBM T.J. Watson Research Center. His research interests
include architecture and software approaches to address power,
reliability, and thermal issues for embedded and high-performance
computer systems. |
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Website |
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PHOTOS Courtesy of Tin Tin Wee |
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