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Technical
Seminar
Distinguished Lecturer Series |
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Performance Enhancement Techniques for Fractional-N
PLLs |
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DATE/TIME
Thursday, March 27, 2008 (4:30pm to 6:30pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 4:15pm for security sign-in and escort.
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT |
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This talk provides a tutorial-level
explanation of fractional-N
PLLs for frequency synthesis followed by a description of
recently-developed techniques that can be used to enhance their
performance. The tutorial portion of the talk briefly reviews
integer-N PLLs and then
explains the additional ideas and issues associated with the extension
to fractional-N PLLs.
Topics include a self-contained explanation of the relevant aspects of
ΔΣ modulation, and non-ideal effects of particular concern in
fractional-N PLLs such as
charge pump nonlinearities and data-dependent divider delays. Then, a
charge pump linearization technique and an adaptive phase noise
cancellation technique are presented, including implementation details
and experimental results associated with a 2.4 GHz ISM-band fractional-N
PLL CMOS integrated circuit. |
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REFERENCES |
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IEEE ISSCC Dig. Tech. Papers, pp. 78-79, Feb 2002.
(copyright by IEEE)
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B. Miller and B. Conley, “A multiple
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B. Miller and B. Conley, “A multiple
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T.A. Riley, M.A. Copeland, and T.A.
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and Systems, pp.1310-13, May 1993. (copyright by IEEE)
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L. Tee, and P.R. Gray, "A 1.4 GHz differential
low-noise CMOS frequency synthesizer using a wideband PLL
architecture",
IEEE
ISSCC Dig. Tech. Papers,
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S. Pamarti, L. Jansson, and I. Galton, “A
wideband 2.4-GHz delta-sigma fractional-NPLL with 1-Mb/s
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frequency synthesizer with 5us
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A. Swaminathan, K. Wang, and I. Galton, “A
Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with
Adaptive Phase-Noise Cancellation,”
IEEE ISSCC Dig. Tech. Papers,
vol. 50, Feb. 2007. (copyright by IEEE)
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no. 4, pp. 966-980, Apr. 2006. (copyright by IEEE)
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ISSCC Dig. Tech. Papers, Feb. 2006. (copyright by IEEE)
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PROF.
IAN GALTON (University of
California, San Diego, CA)
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Ian
Galton received the ScB degree from Brown University in 1984, and the
MS and PhD degrees from the California Institute of Technology in
1989 and 1992, respectively, all in electrical engineering. Since
1996, he has been a professor of electrical engineering at the
University of California, San Diego where he teaches and conducts
research in the field of mixed-signal integrated circuits and systems
for communications. Prior to 1996, he was with UC Irvine, and
prior to 1989, he was with Acuson and Mead Data Central. In
addition to his academic research, he regularly consults at several
semiconductor companies and teaches industry-oriented short courses on
the design of mixed-signal integrated circuits. |
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He has served on a corporate Board of
Directors, on several corporate Technical Advisory Boards, as the
Editor-in-Chief of the IEEE Transactions on Circuits and Systems II:
Analog and Digital Signal Processing, on the IEEE Solid-State Circuits
Society Administrative Committee, on the IEEE Circuits and Systems
Society Board of Governors, on the IEEE International Solid-State
Circuits Conference Technical Program Committee, and in the IEEE
Solid-State Circuits Society Distinguished Lecturer Program. |
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Website |
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PHOTOS Courtesy of Tin Tin Wee |
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