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Technical
Seminar
Distinguished Lecturer Series |
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New Dimensions in Microarchitecture - 3D Integration
Technology |
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DATE/TIME
Tuesday, September 9, 2008 (3:15pm to 4:30pm) |
PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 3:00pm for security sign-in and escort.
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COST
Free. As always, food &
drinks will be provided. |
RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT |
Despite generation on
generation of scaling, computer chips have remained essentially
2-dimensional. Improvements in on-chip wire delay and in the total
number of inputs and outputs have not been able to keep up with
improvements to the transistor, and it's getting harder and harder to
hide it! 3D chip technologies come in a number of flavors, but are
receiving lots of attention lately as a means of extending CMOS
performance. Designing for three dimensions, however, forces us to
look at formerly-two-dimensional integration issues quite differently.
IBM as well as other companies and research institutions are developing
ways of addressing these challenges. This talk follows
announcements from IBM noting our development of this breakthrough
technology and its appearance on IBM’s technology roadmap. This
talk will introduce 3D concepts and their architectural value, and will
offer a number of movies and animations showcasing some of the
capabilities that 3D-enabled computing may offer in the future. |
PRESENTATION SLIDES
pdf |
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KERRY
BERNSTEIN (IBM T.J. Watson Research Center, Essex Junction, VT)
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Kerry Bernstein is a
Senior Technical Staff Member at the IBM T.J. Watson Research Center,
Yorktown Heights, NY. He is currently responsible for future
product technology definition, performance, and application. He
has been privileged to be on the teams developing and introducing
fundamental device and interconnect technologies to the industry during
his career, including NMOS, CMOS, Partially-Depleted
Silicon-On-Insulator devices, and copper/Low-K interconnects. Mr.
Bernstein received the B.S.E.E. degree from Washington University in St.
Louis, MO, and joined IBM in 1978. He holds 87 US Patents and is a
co-author of three college textbooks and multiple papers on high-speed
computing. Mr. Bernstein is an IEEE Fellow. He is also a
Captain and executive officer in the Vermont State Guard. Mr.
Bernstein and his wife have three children, and live in Underhill, VT. |
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