|
 |
|
|
Technical
Seminar |
|
|
|
|
|
Layout-Dependent Proximity Effects in Deep Nanoscale
CMOS |
|
|
DATE/TIME
Thursday, April 16, 2009 (4:30pm to 6:00pm) |
|
PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
|
|
DIRECTIONS
|
|
From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 4:15pm for security sign-in and escort. |
|
COST
Free. As always, food &
drinks will be provided. |
|
RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
|
|
ABSTRACT |
|
As CMOS is scaled into the nanometer range, we
must model not only the intrinsic MOSFET, but also how its
implementation in layout affects device performance. Layout proximity
has already become relevant at the 130nm node due to shallow trench
isolation stress and well implant mask scattering on active regions.
Proximity becomes even more important with the advent of mechanical
strain engineering, which introduces intentional stressors (such as
nitride liners, embedded SiGe, and stress memorization) to boost device
channel mobilities. Unfortunately, this complicates MOSFET modeling
because device performance now depends on both the layout of the MOSFET
and its local neighborhood. All these effects will cause a delta between
pre-layout schematic based simulations and those based on layout
extraction. The prudent designer needs to be aware of these effects so
s/he can provide guidance during the physical implemetation phase of the
design. |
|
This talk will review
some of the major layout-dependent proximity effects in nanoscale CMOS.
A set of models and tools was devised to evaluate these effects in AMD's
45nm and 32nm SOI CMOS process. A novel feature of the tool set is the
ability to evaluate proximity effects during initial layout placement. A
methodology for accounting for proximity effects in standard cell
libraries, which have an uncertain neighborhood, will also be discussed. |
|
PRESENTATION SLIDES
pdf |
|
|
DR. JOHN FARICELLI (AMD, Boxborough, MA)
|
 |
John Faricelli received his BSEE from
Rensselaer Polytechnic Institute, Troy, NY, in 1978, and his PhDEE
in electrophysics from Cornell University, Ithaca, NY, in 1984.
His doctoral thesis concerned the extraction and modeling of latchup
paths in CMOS. He worked for many years in the area of Technology
CAD (TCAD), applying device and process simulation tools to several
generations of CMOS development. A highlight of his career was
working with Dr. Nadim Khalil on the extraction of two-dimensional
dopant profiles from electrical measurements using the inverse modeling
method. In recent years, he has worked in the areas of compact
device modeling, RC extraction and interconnect modeling, and
electromigration and supply-droop tools. He is currently Senior
Member of Technical Staff at AMD. Dr. Faricelli is an IEEE Senior
Member and has in the past served on the IEDM technical committee. |
|
|
|
|
