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Technical
Seminar |
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Topics in Design and Analysis of High Data Rate
SERDES Systems |
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DATE/TIME
Thursday, September 3, 2009 (3:30pm to 5:30pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter
AMD campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW
corner of Harmony Road and Ziegler Road. Proceed to 3rd floor for
escort to seminar auditorium. Non-AMD
employees: please arrive at 3:15pm for security sign-in and escort. |
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT
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Data communication protocols for memory
subsystems, peripheral interfaces, storage systems, and high data rate
backplane interconnects for servers and network switch gear have evolved
rapidly over the last decade to support the demand for ever increasing
bandwidth. High bandwidth is needed to feed data hungry video, data,
storage, and network processors which have seen exponential increases in
performance provided by advances in integrated circuit and storage
technology. |
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The Serializer/Deserializer (SERDES) is an
ubiquitous building block in these modern data-centric systems. The
SERDES device is responsible for reliably transferring wide parallel
data streams within an integrated circuit over an external serial
channel lane at a data rate multiplied up by the width of the parallel
data. In only the last two years, industry standard serial data rates
have rocketed past 10Gb/s and are quickly approaching 15, 20, 25Gb/s and
higher for backplane and chip-to-chip interconnects. Such high data
rates present large challenges in the design of both passive channel
elements such as IC packages, sockets, board material, and connectors
and the active SERDES devices on the system ICs. |
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This seminar will discuss a range of topics
important in the design and analysis of high data rate SERDES systems in
a tutorial format. Topics which will be covered start with an overview
of N-port s-parameters for efficient modeling and analysis of the
end-to-end serial interconnect channel. The impact of the channel
characteristics on achievable link performance is discussed. Next, a
range of topics which focus on key SERDES subsystems will be presented,
including line equalizer adaptation methods for feed-forward equalizer (FFE),
continuous-time equalizer (CTE), and decision-feedback equalizer (DFE)
techniques, a discussion on asynchronous clock-and-data recovery (CDR)
and associated phase generation subsystem designs including jitter
analysis, and SERDES performance requirements for systems approaching
data rates of 20Gb/s+ including commentary on both classic analog and
ADC based design approaches. |
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PRESENTATION SLIDES
pdf |
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REFERENCES |
- P. Triverio et al., "Stability,
causality, and passivity in electrical interconnect models," IEEE
Trans. Advanced Packaging, vol. 30, no. 4, Nov. 2007, pp. 795-808.
(copyright by IEEE)
- P. Triverio and S. Grivet-Talocia, "Causality-constrained
interpolation of tabulated frequency responses," IEEE Electrical
Performance of Electronic Packagaing, Oct. 2006, pp. 181-184.
(copyright by IEEE)
- T.Toifl et al., "Low-complexity
adaptive equalization for high-speed chip-to-chip communication paths by
zero-forcing of jitter components," IEEE Trans. Communications,
vol. 54, no. 9, Sep. 2006, pp. 1554-1557. (copyright by IEEE)
- "CEI-28G:
Paving the way for 100 Gigabit," Optical Internetworking Forum.
- D. Kam et al., "Is
25Gb/s on-board signaling viable?" IEEE Trans. Advanced Packaging,
vol. 2, no. 2, May 2009, pp. 328-344. (copyright by IEEE)
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TROY BEUKEMA (IBM
Research, Yorktown Heights, NY)
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Troy Beukema received the BSEE and
MSEE degrees from Michigan Technological University, Houghton, in
1984 and 1988, respectively. Throughout his 25 years of industry
experience he has been involved in research and development related to
communication systems. His career began at Hewlett Packard in 1984 with
test instrumentation development, continued at Motorola in 1988 in the
area of cellular radio systems, and since 1996 he has been with IBM
Research in Yorktown Heights, NY where he has focused on both wireless
and wireline system designs in the Communication Technology department.
His most recent activity at IBM is in the area of high data rate SERDES
system designs. He is a recipient of the IBM Outstanding Technical
Achievment award for his work in developing decision-feedback
equalization based SERDES technology which has been applied to a range
of products operating to 10Gb/s data rates and higher. |
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His research interests include high data
rate SERDES system design and analysis, with a focus on realizing high
performance I/O cores in deep submicron CMOS technology for high density
backplane interconnect applications.
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PHOTOS Courtesy of Tin Tin Wee |
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