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Technical
Seminar |
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Tutorial on Copper Interconnect Technology for the 32nm Node and
Beyond |
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DATE/TIME
Thursday, January 28, 2010 (3:30pm to 6:00pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 3:15pm for security sign-in and escort. |
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to
visvesh.sathe@amd.com. |
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ABSTRACT |
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This
tutorial paper is an extended encore of a paper recently presented at
Custom Integrated Circuits Conference
(CICC) 2009.
Copper interconnects have gained wide
acceptance in the microelectronics industry due to improved resistivity
and reliability compared to aluminum interconnects. However, there are
many challenges with implementation of copper interconnects at the 32 nm
node and beyond, including increased resistivity, integration with
porous low-k materials, and reliability. In addition, for RF and mixed
signal technology, integration of passive devices is required. In this
paper, each of these topics is addressed. |
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PRESENTATION SLIDES
pdf |
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REFERENCE |
- J. Gambino, F. Chen, and J. He, "Copper
interconnect technology for the 32nm node and beyond," Proc. IEEE Custom Integrated Circuits Conf., Sep.
2009. paper (copyright by
IEEE)
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DR. JEFF GAMBINO (IBM,
Essex Junction, VT)
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Jeff Gambino
received the BS degree in materials science from
Cornell University, Ithaca, NY, in 1979, and the PhD degree in
materials science from the Massachusetts Institute of Technology,
Cambridge, MA, in 1984.
He joined IBM, Hopewell Junction, NY, in 1984, where he worked on
silicide processes for Bipolar and CMOS devices. In 1992, he joined the
DRAM development alliance at IBM’s Advanced Semiconductor Technology
Center, Hopewell Junction, NY. While there, he developed contact and
interconnect processes for three generations of DRAM products. In 1999,
he joined IBM’s manufacturing organization in Essex Junction, VT, where
he has worked on copper interconnect processes for CMOS logic and CMOS
imager technology. He has published over 100 technical papers and
holds over 100 patents. |
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