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Technical Seminar |
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| SEMINAR 1:
Optical Biosensors (Colorado State University Student
Presentation) |
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| SEMINAR 2:
Constant-Current Threshold Voltage Extraction in HSPICE for
Nanoscale CMOS Analog Design |
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DATE/TIME Thursday,
June 3, 2010 (3:30pm to 5:00pm) |
| PLACE
AMD Fort Collins Campus
(Fort Collins, CO)
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DIRECTIONS
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From
I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler
intersection. AMD is located on the NW corner of Harmony
Road and Ziegler Road. Proceed to 3rd floor for escort to
seminar auditorium. Non-AMD
employees: please arrive at 3:15pm for security sign-in
and escort. |
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COST
Free. As always,
food & drinks will be provided. |
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RSVP
Send e-mail to
visvesh.sathe@amd.com. |
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SEMINAR 1 ABSTRACT |
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Mohamed Eldeiry, Wesley Fuller, Torsten Kiljan, Ashley Miller,
Liesel Mundhenke, Mujahid Naqbi,
Prof. Kevin Lear
(Advisor) |
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This Senior project was recently selected as winner of the Best
Paper Contest. The award will be presented to the student
winners at the beginning of the meeting, followed by a 20-minute
student presentation of the work. |
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Medical diagnostic equipment for early detection of human and
canine cancers are of great interest. The proposed optical
biosensor is an inexpensive microfluidic chip aimed at detecting
cancer cells based on their optical properties. Using
dielectrophoretic (DEP) forces, cells are directed to a region
in the chip where they are held stationary while a spectral
analysis is performed on them to determine if they cancerous.
Based on the results of the spectral analysis, cancerous cells
can be sorted and collected all while maintaining their original
state for further analysis. This year, the senior design team
successfully automated the collection of individual cell spectra
using this chip. The complex nature of the project
required collaborative interdisciplinary efforts in order to
make the system more robust and practical. Through successful
management and collaboration between biomedical, chemical, and
electrical engineers, automation of the system was accomplished
this year allowing for hundreds of cells to be processed with
the device. This was achieved by optimizing electrode
components, creating circuitry for trapping and switching,
customizing user interfaces in software for controlling the
hardware, optimizing the microfluidic behavior in the channel,
and assessing the physiology of the cellular components as they
are processed in the device. |
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PRESENTATION POSTER
gif |
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SEMINAR 2 ABSTRACT |
| Alvin
Loke, Zhi-Yuan Wu, Reza Moallemi, Dru Cabler, Chad Lackey, Tin
Tin Wee, and Bruce Doyle |
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This part-tutorial paper was recently presented
at the
Synopsys Users Group (SNUG) San Jose 2010 Conference and
received the Best Paper and Best First-Time Presenter awards. |
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present a new HSPICE feature that extracts MOSFET threshold
voltage (VT) based on the constant-current definition
universally adopted by fabs to measure, specify, and monitor VT.
With simulated VT now conveniently correlated to
measurement, this capability enables faster design of robust
analog circuits in cutting-edge CMOS technologies where voltage
margins are critically limited and only predictive models,
subject to periodic retargeting, are available during design.
The feature was developed and evaluated using a 32-nm technology
model and subsequently introduced in the 2009.09 HSPICE release.
Operating point, DC, AC, and most importantly transient analyses
are supported for industry-standard BSIM4, BSIMSOI4, and PSP
MOSFET models. |
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To motivate
this work, we provide a brief tutorial of how the basic MOSFET
has evolved to its modern-day structure, explain how VT
is currently modeled in BSIM4, and summarize practical VT
measurement techniques on silicon. |
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PRESENTATION SLIDES
pdf (copyright by
AMD) |
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REFERENCE |
- A. L. S. Loke, Z.-Y. Wu, R.
Moallemi, C. D. Cabler, C. O. Lackey, T. T. Wee, and B. A.
Doyle, "Constant-Current Threshold Voltage Extraction
in HSPICE for Nanoscake CMOS Analog Design," in Synopsys
Users Group (SNUG) 2010 Conference (San Jose, CA), Mar.
2010. (copyright by AMD)
paper
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DR.
ALVIN LOKE (AMD, Fort Collins, CO) |
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Alvin
Loke
(S’89–M’99–SM’04) received the BASc degree in engineering
physics with highest honors from the University of British
Columbia, Vancouver, Canada, in 1992, and the MS and PhD degrees
in electrical engineering from Stanford University, Stanford,
CA, in 1994 and 1999 respectively. He was recipient of the
Canadian NSERC 1967 Graduate Scholarship and his doctoral
research focused on interconnect integration and reliability of
copper and low-K dielectrics. He has interned at Sumitomo
Electric Industries (Osaka, Japan), Texas Instruments (Dallas,
TX), and Motorola (Austin, TX). After graduating, he worked for
several years on technology integration at Hewlett-Packard
Laboratories (Palo Alto, CA) and at Chartered Semiconductor
Manufacturing (Singapore) as an Agilent (now Avago) Technologies
assignee. He later transferred to Fort Collins, CO, to design
SerDes PLL/DLL circuits. |
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In 2006, Alvin
joined Advanced Micro Devices where he is a Senior Member of
Technical Staff designing wireline circuits and architectures as
well as interfacing with technology groups on
analog/mixed-signal concerns. He has authored several dozen
technical publications and holds ten patents. Since 2003, he has
chaired and remains active in the Fort Collins SSCS Technical
Chapter which received the Outstanding Chapter Award in 2005. He
has been on the CICC technical program committee since 2006 and
serves on the ECE Department Industrial Advisory Board of
Colorado State University (recently as President) and on the
SSCS Chapters committee. |
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