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Technical
Seminar |
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The Future of Electrical I/O for Microprocessors |
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DATE/TIME
Friday, October 22, 2010 (10:00am to 12:00pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 9:45am for security sign-in and escort.
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to
visvesh.sathe@amd.com. |
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ABSTRACT |
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High-speed CMOS
microprocessor I/O has scaled aggressively over the past decade in terms
of power and performance largely due to advances in equalization and
clocking techniques. Future multi-core processors will likely require
I/O bandwidth exceeding 1TB/s along with dramatically improved power
efficiency. However, there has been some question about whether
electrical I/O will continue to satisfy chip-to-chip communication
requirements over the next decade. This presentation describes how
electrical signaling techniques can be scaled in terms of power,
performance, and density to enable the next several generations of
microprocessor-based systems and applications. Innovative circuit
architectures will facilitate link energy efficiency better than 1pJ/bit
while mitigating the increasing variation within scaling CMOS processes.
Transitioning from legacy channels to new interconnect topologies and
materials will significantly improve the power/performance/density
tradeoff. Statistical link-level design tools that allow designers to
rapidly quantify high-level architecture tradeoffs will promote balanced
link designs that co-optimize power, performance, and channel topology.
To support these link scaling predictions, the design and measurement
results for a recent 470Gb/s chip-to-chip link prototype operating with
1.4pJ/bit energy efficiency will also be discussed. |
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PRESENTATION SLIDES
pdf |
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DR. FRANK
O'MAHONY (Intel, Hillsboro,
OR)
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Frank O’Mahony received
the BS, MS, and PhD degrees in electrical engineering from
Stanford University in 1997, 2000, and 2004, respectively. Since 2003,
he has been with Intel’s Circuit Research Laboratory in Hillsboro, OR.
His research at Intel focuses on high-speed and low-power data links,
clock generation and distribution, and design techniques for low-noise,
variation-tolerant clocking and signaling circuits. Frank has received
the ISSCC Jack Kilby Award and the TCAS Darlington Best Paper Award. |
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CHAPTER SPONSORS |
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