IEEE Solid-State Circuits Society

DENVER SECTION

Home

Upcoming Events

Past Events

Technical Seminar

Extending HyperTransport™ Technology to 8.0 Gb/s in 32-nm SOI-CMOS Processors

DATE/TIME Friday, January 20, 2012 (10:00am to 11:00am)

PLACE AMD Fort Collins Campus (Fort Collins, CO)

DIRECTIONS

From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD campus on right immediately following Harmony/Ziegler intersection. AMD is located on the NW corner of Harmony Road and Ziegler Road. Proceed to 3rd floor for escort to seminar auditorium. Non-AMD employees: please arrive at 9:45am for security sign-in and escort.

COST Free. As always, food & drinks will be provided.

RSVP Send e-mail to https://gomartin.net/sscs/2012/rsvp_2012_01_20.htm

ABSTRACT

This presentation is an extended encore of a contributed paper delivered at the 2011 Asian Solid-State Circuits Conference (A-SSCC) in Jeju, Korea.

We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>200 MHz) PLL to attenuate high-frequency jitter in the received forwarded clock and redesigned power-hungry circuits to operate at 8.0 Gb/s within the existing 45-nm package thermal limit.

PRESENTATION SLIDES pdf (IEEE copyright)

REFERENCE A-SSCC paper (IEEE copyright)

BRUCE DOYLE (AMD, Fort Collins, CO)

Bruce Doyle (M’84) received the BSEE degree from Carleton University, Ottawa, Canada in 1984. Since 1984, he has been involved in the design of memories, graphics processors, analog circuits, mixed-signal IC’s, high-performance microprocessors, and leading edge IO technologies. From 2002 to 2006, he worked for Hewlett-Packard / Intel in Fort Collins, CO, on the Itanium family of high-performance microprocessors as a physical designer in high-speed I/Os, clocking, and thermal systems. Currently, he is a Principal Member of Technical Staff at Advanced Micro Devices in the Mile High Design Center, Fort Collins, CO, where he is focused on developing next generation IO technology focused on lower power I/Os and optical interconnect systems. His expertise includes I/O design, high-speed circuit design, analog circuit design, and mixed-signal verification. He holds 12 US patents and has published 8 technical/conference papers. He currently serves as Chair of the Fort Collins IEEE Solid-State Circuits Society technical chapter and as a technical reviewer of IEEE journals such as the Journal of Solid-State Circuits.