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Officers
- 2006 |
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ALVIN LOKE
- Chair,
IEEE Senior Member
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Alvin Loke received his
B.A.Sc. (Eng. Physics) degree with highest honors from the University of British Columbia,
Vancouver, Canada, in 1992, and the M.S.E.E. and Ph.D.E.E. degrees from Stanford University, Stanford, CA, in 1994 and
1999 respectively. He was recipient of the Canadian NSERC 1967 Graduate
Scholarship. While at Stanford, his research focused on
interconnect process integration issues with copper and low-K polymer
dielectrics. Dr. Loke is author/co-author in over 20 technical
publications, and three patents with several pending. He held internships at Texas
Instruments (Dallas, TX), Motorola (Austin, TX), and at Sumitomo
Electric Industries (Osaka, Japan). In 1998, he joined Hewlett-Packard Laboratories,
Palo Alto, CA where he was involved in process integration of deep
submicron ferroelectric memory for embedded applications.
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In
1999, when Agilent Technologies divested from Hewlett-Packard, he was on assignment in Chartered Silicon Partners, Singapore, as Senior
Process Integration Engineer engaged in copper and local interconnect module integration. In 2001, he
transferred to Fort Collins, CO
where he developed CMOS mixed-signal phase-locked
loop circuits for low-jitter embedded SerDes I/O and ASIC core clocking.
In 2006, he joined the Mile High Design Center of Advanced Micro Devices
in Fort Collins, CO, as Senior Member of Technical Staff.
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BOB
BARNES - Vice Chair & Treasurer,
IEEE Senior Member
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Bob Barnes received his B.S.E.E. degree (summa
cum laude) from Washington State University, Pullman, WA, in 1980, and
the M.S.E.E. degree from Stanford University, Stanford, CA, in 1987.
Prior to his undergraduate studies, he served in the United States Air
Force as an Electronics Technician repairing and maintaining
ground-based navigation transmitters. He joined Hewlett-Packard's Disk
Memory Division, Boise, ID, in 1980 where he worked on disk drive
head/servo characterization, and advanced read channel designs. In
1996, he joined Hewlett-Packard's (now Avago Technologies') integrated
circuits design center in Fort Collins, CO where he is currently a
Senior Design Engineer developing 90nm and 65nm CMOS mixed-signal phase-locked
loop architectures and circuits for low-jitter embedded SerDes I/O
applications. He holds five patents in areas of disk drive and IC
design, with several pending. |
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TIN TIN WEE -
Secretary & Webmaster,
IEEE Senior Member |
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Tin Tin Wee received her B. Tech. (Electronics Eng.)
from the National University of Singapore, Singapore, in 1999. Prior
to receiving her B. Tech., she was an Associate Engineer at International
Video Products, Singapore, where she involved in RF test, measurement, and
failure analysis of consumer video electronics. In 1996, she joined Chartered Semiconductor
Manufacturing, Singapore, as Process Integration Engineer where she was
engaged in multiple aspects of 0.25um, 0.18um, and 0.15um technology
development and transfer. Activities included SRAM development,
yield enhancement, and most recently, copper and local interconnect module
integration. Ms. Wee returned to the National University of
Singapore to study circuits and systems, and completed her M.S.E.E. degree
in 2001.
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In 2004, she
joined Agilent Technologies (now Avago
Technologies) where she was involved in bench test, characterization, and
debug of 130nm and 90nm CMOS ASIC's with low-jitter embedded SerDes and core clocking
PLL's. In 2006, she joined the Mile High Design Center of Advanced
Micro Devices in Fort Collins, CO. She hold two patents.
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Officers for Past Years
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