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WMED 2011 Technical Program
Friday, April 22nd, 2011 8:00AM-6:00PM
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8:00 AM
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Check In and Door Registration
With Continental Breakfast
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8:30 AM
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Welcome to WMED 2011
Room: Simplot BD
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8:45 AM
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Keynote Address:
“Atoms to go…..Ionic Memory and Data Storage”
Prof. Michael N. Kozicki, Adesto Technologies
Room: Simplot BD
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9:45 AM
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Break and Poster Setup
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10:00 AM
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Invited Tutorials (Parallel sessions)
Tutorial 1: “Advanced CMOS Transistor Technology: Past, Present and Future”
Prof. Suman Datta, Penn. State
Room: Simplot BD
Tutorial 2: “Energy Efficient Multi-Gb/s I/O: Circuit and System Design Techniques”
Bryan Casper, Intel Circuit Research Labs
Room: Simplot C
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NOON
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Buffet Luncheon
Provided by WMED
Room: Hatch
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1:00 PM
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Invited Talk: “Promises and Challenges in Light-Emitting Diodes for Lighting Applications”
Prof. E. Fred Schubert, RPI
Room: Simplot BD
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2:00 PM
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Invited Talk: “Label-Free Biosensing with Silicon Nanowires”
Prof. Mark A. Reed, Yale University
Room: Simplot BD
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3:00 PM
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Break
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3:15 PM
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Contributed Papers (Parallel Sessions)
Session 1 Process and Device
Room: Simplot BD
Session 2 Solid State Circuits
Room: Simplot C
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5:30 PM
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Poster Presentation and Refreshments
Room: Hatch
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Contributed Papers
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Session 1
Room: Simplot BD
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3:15 PM
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“Structural Study of Ag-Ge-S Solid Electrolyte Glass System for Resistive Radiation Sensing”
P. Chen, M. Ailavajhala, M. Mitkova, D. Tenne, Boise State University; I. Sanchez Esqueda, H. Barnaby, Arizona State University
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3:35 PM
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“Friction Based Endpoint Technique for Barrier Polish During CuCMP”
S. Zhu, J. Hofmann, A. Jindal, Micron Technology, Inc.
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3:55 PM
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“Finite Element Modeling of a Back Grinding Process for Through Silicon Vias”
A. H. Abdelnaby, G. P. Potirniche, F. Barlow, A. Elshabini, University of Idaho; R. Parker, Micron Technology, Inc.
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4:15 PM
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“VT statistics on nanoscale NAND Flash arrays”
A. Spessot, A. Calderoni and P. Fantini, Micron Technology, Inc.
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4:35 PM
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“High-Performance Transistor Evaluation for Low-Cost Embedded DRAM”
H. Furusawa, S. Nogami, T. Ogawa, M. Kumazaki, N. Okada and H. Yamamoto, Micron Technology, Inc.
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Session 2
Room: Simplot C
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3:15 PM
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“Self-Calibrating Continuous-Time Equalization with Multiple Degrees of Freedom”
T. M.. Hollis, Micron Technology, Inc.
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3:35 PM
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“Adjustable supply voltages and refresh cycle for process variations and temperature changing adaptation in DRAM to minimize power consumption”
L. Tran, F. J. Kurdahi, and A. M. Eltawil, University of California Irvine.
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3:55 PM
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“All digital duty-cycle correction circuit design and its applications in high-performance DRAM”
F. Lin, Micron Technology, Inc
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4:15 PM
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“A Non-Volatile Memory Array Based on Nano-Ionic Conductive Bridge Memristors”
S. Wald, J. Baker, M. Mitkova, N. Rafla, Boise State University
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Poster Session and Refreshments
Room: Hatch
Time: 5:00 PM
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“Optimized Germanium Co-Implant with B2H6 PLAD for Better Advanced PMOS Device Performance”
J. L. Liu, S. Qin, J. Hu, A. Mcteer, Micron Technology, Inc
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“Design of low noise CMOS charge pump with adjustable output voltage and adjustable power”
S. A. Stickel, Boise State University
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“Measurement and Simulation of Various Geometries of LTCC Electron Hop Funnels”
T. Rowe, J. Browning, Boise State University
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“Efficient Design and Synthesis of Decimation”
R. M. R. Koppula, S. Balagopal, V. Saxena, Boise State University
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“A Novel Material Solution for Non Volatile Contact Bridge Memristive Memory Fabrication”
M. R. Latif , E. Coleman, M. Mtikova, P. Chen, Boise State University, and G.S. Tompa, Structured Materials Industries, Inc Piscataway, NJ USA
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“Radiation induced effects in pure and Ag doped Ge-Se films”
M. S. Ailavajhala, P. Chen, M. Mitkova, Boise State University, and H. Barnaby, Arizona State University
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“Design Techniques for a 70 Gbps CMOS Multiplexer”
P. Osheroff, G. S. La Rue, Washington State University
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Workshop Sponsors
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Boise Section
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Boise Chapter
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