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3D Modeling of Microelectronic Structures in R&D

A. Gruszka and J. Jozwiak
Micron Technology, Incorporated
Boise, ID, USA

Abstract:

The poster will discuss how sophisticated modeling software is used in the Micron R&D organization to produce process-accurate three-dimensional models of complicated memory devices and structures on silicon wafers. Recent generations of memory technologies utilize devices that are very difficult to visualize using two-dimensional diagrams. The software generates the models from two input sources: a 2D layout file, and a step-by-step description of the process flow. The resulting models can be examined in multiple ways including enlarging, rotating, cutting arbitrary cross sections, and rendering selected layers invisible to see underlying detail. The models are used by the organization in the following ways:

• They are directly viewed and manipulated by engineers designing the process to clearly visualize the final structures and make needed process changes.
• The models are captured in still images and incorporated into comprehensive training documents that help the entire organization better understand the complexities of the technology.
• The models can (and have) been used to identify weak points in the structures, or oversights in the process flow, allowing for corrections to be made before expensive silicon is used.
• The process flow is applied to non-die structures, such as alignment marks and test structures, to predict how these structures will be formed, again allowing for corrections to be made. This can save both the expenses of silicon and masks.

This workshop is receiving technical co-sponsorship support from the IEEE Electron Devices Society.

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