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Invited Talk - 2.5D and 3D Technology Advancements for Systems

Dr. John U. Knickerbocker, IBM T. J. Watson Research Center

Abstract:

Silicon interposer packaging and thin die stacking technologies with through-silicon-vias (TSV’s) can improve performance, increase bandwidth, improve power efficiency, and reduce costs for systems applications. Proper system architecture and designs are critical to achieve these system benefits using silicon interposer packaging (2.5D) and 3-dimensional (3D) die stacking technologies. 2.5D and 3D heterogeneous multi-chip integration technologies have numerous challenges but through advancements they each can provide significant system benefits when compared to traditional packaging integration solutions. Portable electronics such as smart phones, sensors and bio-medical systems can benefit from “technology miniaturization” with increasing function in product generations, improved power efficiency, lower cost and high volume scale up capability associated with this small size and wafer or panel level processing. Large systems can also benefit from 2.5D and 3D technologies by taking advantage of close proximity computing, higher bandwidth with low latency, and power efficiencies to achieve higher performance and lower energy per operation.

2.5D and 3D technology advancements have addressed materials, structures and processes for device wafer fabrication with TSV’s, wafer thinning and backside processing. 3D integration technology advancements have also addressed assembly, test, module integration and thermal challenges to support first generation of manufacturing products and position for next generations of more complex products. In these cases, materials and structures have been developed through manufacturing processes and equipment to provide design ground rules that support system clocking, power distribution and signal integrity. Electrical models simulate equivalent measured characteristics of TSV’s and silicon to silicon micro-interconnections such as solder micro-bumps or micro-pillars. Device wafer fabrication processes with TSV compatible fabrication, wafer thinning and backside processing were developed. Die integration through die to die, die to wafer or wafer to wafer bond, assembly, test methods have been advanced through module integration demonstrations. Fine pitch and high power test demonstrations are in progress to support known good die (KGD) and high yield assembly for integrated 2.5D and 3D modules. Thermal technology and models have addressed temperature profiles of the active devices in 3D structures to manage potential hot spots and remove heat efficiently to avoid system reliability issues due to excessive thermal or thermal-mechanical stress.

This research paper compares 2.5D and 3D technologies for systems, numerous challenges overcome including wafer processing with TSV’s and multi-die integration advancements. Data are reported from multiple electrical and thermal hardware demonstrations. 2.5D technology hardware designs, build and characterization demonstrations have been made using from 2 to 4 chip integration modules to over 30 chips per integration module. Results show low power chip to chip electrical link connectivity can be achieved with silicon interposer technology for wiring channels at 10Gbps and up to 50 mm using fine pitch 25um diameter solder interconnections and low power transmit and receive circuits. Results also show low complexity and highly complex hardware assemblies can be integrated into modules with 200um pitch to 50 um pitch full area array solder interconnections. Multiple 3D two to four high die stack technology designs, build and characterization demonstrations have also been made. Results show successful operation of multi-high functional die stacks. Multiple thermal die stack test vehicles were successfully designed, fabricated and characterized. Results showed methods to improve heat transport by considering the die structure and interconnection density and pitch in a multi-high die stack with TSV’s.

Speaker’s biography:

Dr. Knickerbocker is an IBM Distinguished Engineer. He is the manager of 3D Technology Integration at IBM Research. He received his PhD degree in 1982 from the University of Illinois studying Materials Science & Engineering. He has 30 years experience in IBM Microelectronics Research and Development. For his first 20 years at IBM, Dr. Knickerbocker has lead advanced packaging technology development for ceramic and organic packaging, flip chip die attach to single and multi-chip modules, print wiring board technology, module to board assembly and liquid or air thermal cooling solutions at IBM Microelectronics in East Fishkill. In the most recent 10 years at IBM, he has managed 3D silicon integration at IBM Research. This research has included development of through-silicon-via (TSV) technology, development of wafer support systems for wafer thinning and backside processing, development of silicon interposer packaging technology with TSV’s, development of 3D thin die stacking technology with TSV’s and fine pitch, area array interconnections, heterogeneous die integration technology and power efficient technologies, 3D thermal solutions, electrical, mechanical, physical and thermal characterization and modeling. The research has included demonstrations for high performance computing applications, portable wireless “miniature” microelectronics systems and bio-medical applications. He has authored or co-authored over 200 patents or patent applications and more than 70 technical papers and publications. He serves as a member of the SEMATECH 3D working group and is an active member of IEEE Technical Society in Advanced Packaging Technology.

This workshop is receiving technical co-sponsorship support from the IEEE Electron Devices Society.

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