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FinFET Variability and its Impact on Digital and Analog Circuits (Invited)

V. Moroz
Synopsys Corporation
Mountain View, CA, USA

Abstract:

Transistor variability is a key factor standing in the way of reducing power consumption in mobile devices. Typical three sigma Vt value for a narrow 28 nm planar MOSFET exceeds 150 mV. The circuit has to be able to handle the entire transistor population, ranging from the leaky transistors with low Vt to the hard-to-turn-on transistors with the high threshold. The low threshold side of the distribution is defined to meet the static power consumption spec and the high threshold side of the distribution defines the minimum possible power supply voltage Vdd. Any reduction in the threshold distribution width directly translates into reduction of Vdd, which affects dynamic power consumption as Vdd2. The dominant threshold variability mechanism for planar MOSFETs is random dopant fluctuations (RDF). For the first generation of FinFETs with doped channel, the RDF is still present, but at significantly suppressed level due to the tighter gate control. However, several new FinFET-specific variability mechanisms enter the picture. Subsequent FinFET generations with undoped channel will experience rise and fall of the major variability mechanisms, notably those related to geometry and patterning fidelity. The impacts of FinFET variations on the digital and analog circuits are substantially different. These differences define the distinct approaches in handling variability in analog and digital circuit design.

Speaker’s biography:

Dr. Victor Moroz is a Synopsys Scientist, engaged in a variety of projects on modeling 3D ICs, transistor scaling, FinFETs, stress engineering, solar cell design, innovative patterning, random and systematic variability, junction leakage, non-Si transistors, and atomistic effects in layer growth and doping. Several facets of this activity are reflected in three book chapters and over 100 technical papers, invited presentations, and patents. Has been involved in technical committees at ITRS, IEDM, SISPAD, DFM&Y, ECS, IRPS, and ESSDERC.

This workshop is receiving technical co-sponsorship support from the IEEE Electron Devices Society.

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