IEEE AP/CAS/ED/MTT/SSC Webinar (Virtual) Seminar

Title: Evolution of Load-Store Interconnects to 64.0 GT/s with PAM-4 signaling

Speaker: Debendra Das Sharma (Intel Corporation, Santa Clara, CA)

Date:Friday, August 27, 2021 @ 8:00-9:30am PDT

Cost: Free

RSVP (optional): https://events.vtools.ieee.org/event/register/279739

Abstract:
This talk delves into the taxonomy of interconnects and defines the characteristics of Load-store interconnects such as PCI ExpressR (PCIeR) technology as the basic building block of a wide variety of load-store interconnects. We show where these interconnects are deployed in data centers and on a typical server platform. We explain the layering approach of PCIe and how PCIe specification has been doubling the data rate every generation in a backwards compatible manner every two to three years in power-efficient and cost-effective manner. We will delve deep into PCIe 6.0 specification which adopts PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach of prior generations. A Forward Error Correction (FEC) mechanism will offset the high BER of PAM-4. A new flit-based approach with a light-weight, low-latency FEC coupled with a strong CRC and a low-latency Link level retry mechanism to meet the stringent low-latency, high bandwidth, and high reliability goals. We will explain how other ultra-low latency load-store interconnects with coherency and memory semantics will transition to the 64.0 GT/s with PCIe 6.0 PHY without impacting their latency. A micro-architectural diagram with details of FEC and CRC circuit implementations will delineate the implementation aspects. We also present a new low-power state that ensures power consumption is proportional to bandwidth usage without impacting the traffic flow across all load-store interconnects.

Speaker biography:
Dr. Debendra Das Sharma is an Intel Fellow in the Data Platforms Group and director of the I/O Technology and Standards Group at Intel Corporation. He is responsible for delivering Intel-wide critical interconnect technologies in Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Intel¡¦s Coherency interconnect, and multichip package interconnect. He is a key driver of external standards for PCIe and CXL, and internal proprietary interfaces, as well as implementation. Dr. Das Sharma joined Intel in 2001 as a technical lead in the Advanced Components Division, designing server chipsets. He previously worked with Hewlett-Packard, where he led development of their server chipsets. He holds 134 US patents and is a frequent keynote speaker, invited speaker, and panelist at the PCI-SIG Developers Conference, CXL consortium events, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Storage Developers Conference, and Intel Developer Forum. Dr. Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium and co-leads the CXL Technical Task Force. Dr. Das Sharma has a bachelor¡¦s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst.? He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur.