Title: Hybrid PLL Architectures and Implementations

Speaker: Daniel Friedman
IBM T. J. Watson Research Center (Yorktown Heights, NY)
Past IEEE Solid-State Circuits Society Distinguished Lecturer

Date: Thursday, September 26, 2019 from 3:00 PM to 4:30 PM

Agenda:
3:00 - 3:10pm Sign-in and networking 3:10 - 4:30pm Seminar and Q&A

Location: Qualcomm AZ-Auditorium (10155 Pacific Heights Blvd, San Diego, CA 92121)
Non-Qualcomm attendees: Please arrive 10-15 minutes early to find street parking or in nearby Qualcomm parking structures.

Cost: Free

Abstract:
Depending on the target application and on implementation constraints, both conventional charge pump PLLs and high performance digital PLLs may be excellent implementation choices. Each design type offers significant technical advantages while also raising its own set of design challenges. For example, charge pump PLLs naturally provide a feedback signal that is linearly related to phase error, but typically demand the use of a physically large loop filter capacitor if lower loop bandwidths are desired. High performance digital PLLs solve the loop capacitor problem, but may require a high performance time-to-digital converter as part of the feedback linearization solution. This presentation will focus on the exploration of a hybrid PLL architecture, an approach which features an analog proportional path in combination with a digital integral path, thus in some way offering the best of both PLL worlds. The approach will be introduced and explored through the presentation of multiple high-performance integrated hybrid PLL implementations in deep submicron CMOS technologies.

Speaker bio:
Daniel Friedman is currently a Distinguished Research Staff Member and Senior Manager of the Communication Circuits and Systems department of the IBM Thomas J. Watson Research Center. He received his doctorate from Harvard University and subsequently completed post-doctoral work at Harvard and consulting work at MIT Lincoln labs, broadly in the area of image sensor design. After joining IBM, he initially developed field-powered RFID tags before turning to high data rate wireline and wireless communication. His current research interests include high-speed I/O design, PLL design, mmWave circuits and systems, and circuit/system approaches to enabling new computing paradigms. He was a co-recipient of the Beatrice Winner Award for Editorial Excellence at the 2009 ISSCC, the 2009 JSSC Best Paper Award, the 2017 ISSCC Lewis Winner Outstanding Paper Award; and the 2017 JSSC Best Paper Award; he holds more than 50 patents and has authored or co-authored more than 75 publications. He was a member of the BCTM technical program committee from 2003-2008 and of the ISSCC international technical program committee from ISSCC 2009 through ISSCC 2016; he served as the Wireline sub-committee chair from ISSCC 2012 through ISSCC 2016. He has served as the ISSCC Short Course Chair from 2017 to the present, and is a member of the SSCS Adcom since 2018.