IEEE AP/CAS/ED/MTT/SSC Seminar

Title:
Adaptive and Resilient Circuits for Improving Processor Performance, Energy Efficiency, and Yield

Speaker: Keith Bowman
Date: November 7, 2018 from 10:00 AM to 11:45 AM

Agenda:
10:00-10:15 Sign-in and networking
10:15-11:45 Seminar (with Q&A after seminar)

Location: Qualcomm Q Auditorium (6455 Lusk Blvd, San Diego, CA 92121)
Non-Qualcomm attendees: Please arrive 10-15 minutes early to find street parking or in nearby Qualcomm parking structures.

Cost: Free

Topic Info:
Dynamic device, circuit, and system parameter variations degrade processor performance, energy efficiency, and yield across all market segments, ranging from small embedded cores in an Internet of Things (IoT) device to large CPUs in multicore servers. This seminar introduces the primary variations during the processor operational lifetime, including supply voltage droops, temperature changes, transistor aging, and workload fluctuations. This presentation then describes the negative impact of these variations on processor performance, energy efficiency, and yield. The wide dynamic voltage-frequency scaling (DVFS) range in today’s processors increases these effects. For future IoT edge processors, the low-cost packaging, voltage regulation with time-varying energy harvesters, wide temperature range, and long-lifetime requirements exacerbate these problems further. To mitigate the adverse effects from dynamic variations, this seminar presents adaptive and resilient circuits while highlighting the key design trade-offs and testing implications for product deployment.

Speaker bio:
Keith A. Bowman is a Principal Engineer and Manager in the Processor Research Team at Qualcomm Technologies, Inc. in Raleigh, NC. He is responsible for researching and developing circuit technologies for enhancing the performance and energy efficiency of Qualcomm processors. He pioneered the invention, design, and test of Qualcomm’s first commercially successful circuit for mitigating the adverse effects of supply voltage droops on processor performance, energy efficiency, and yield. He received the B.S. degree from North Carolina State University and the M.S. and Ph.D. degrees from the Georgia Institute of Technology, all in electrical engineering. He previously worked in the Technology Computer-Aided Design (CAD) Group and the Circuit Research Lab at Intel Corporation in Hillsboro, OR. Dr. Bowman has published over 75 technical papers in refereed conferences and journals, authored one book chapter, received 17 patents, and presented over 35 tutorials on variation-tolerant circuit designs. He was the Technical Program Committee (TPC) Chair and the General Conference Chair for ISQED in 2012 and 2013, respectively, and for ICICDT in 2014 and 2015, respectively. Since 2016, he has served on the ISSCC TPC.