Upcoming Event:
Date: Tuesday, September 11, 2012
5:30pm: Networking/light dinner
6:30pm: Presentation
7:45pm: Adjourn
Light Dinner and beverages will be served for a fee. Coffee, tea, and snacks are served free of charge.
Location: LeCroy
3385 Scott Blvd, Santa Clara, CA 95054
Title
TBD
Speaker
Alex McEachern, Power Standards Lab
Abstract
Biography
IEEE SCV-EMC
2012 Mini-Symposium:
Date: October 11, 2012
Venue: Biltmore Hotel Santa Clara
Quick Links:
- Program Agenda
- Registration for Full Program
- Registration for Reception & Exhibits ONLY
- Exhibitors
- Hotel Reservation
Agenda
NOTE: There will be a 30 minute mid-morning and a mid-afternoon refreshment breaks in the exhibit hall.
Registration, Breakfast & Exhibits: 7:30 AM
Morning Session: 8:30 AM - 12:00 PM
ESD Troubleshooting Techniques for Electronic Designs
Presenter: Doug Smith, D. C. Smith Consultants
Tracking down the sources of ESD problems in equipment can be difficult in modern electronic designs. After a brief overview of the characteristics of ESD and its effects on equipment, simple and effective troubleshooting techniques will be discussed that Mr. Smith has developed over many years of solving ESD problems. Live demonstrations will be used to illustrate some of the techniques.
Fundamentals of Signal and Power Integrity
Presenter: Prof. Ege Engin, San Diego State University
As the clock frequencies for off-chip signals approach 20 GHz and beyond, maintaining signal and power integrity are becoming major issues to design a computer system that can actually support such speed. This mini-symposium will cover fundamentals of modeling, simulation, and characterization techniques to ensure signal and power integrity. The following topics will be covered in this tutorial:
- Session 1: Power integrity modeling and design
- Session 2: Signal integrity modeling of losses
- Session 3: Advanced topics: Modeling of through silicon vias for 3D ICs; power plane filtering using electromagnetic bandgap structures.
Session 1: Power integrity modeling and design
Lunch & Exhibits: 12:00 PM - 1:30 PM
Afternoon Session: 1:30 PM - 5:00 PM
Session 2: Signal integrity modeling of losses
Session 3: Advanced topics: Modeling of through silicon vias for 3D ICs; power plane filtering using electromagnetic bandgap structures
Reception & Exhibits: 5:00 PM - 6:00 PM
There will be an exhibition by vendors of EMC design, test and measurement products and services. During the reception in the exhibit area, heavy appetizers and beverages will be available. You are welcome to attend the reception only at NO CHARGE, provided a registration form is submitted in advance. Thus, if you can't join us for the entire day, drop by for the reception and exhibition to network with the speakers and attendees as well as vendors. You might even win a raffle prize! Anyone who ONLY wishes to attend the Reception & Exhibits must register here. The Reception & Exhibits session is also organized as a PACE (Professional Activities Committees for Engineers) event under IEEE-USA.
Biographies
Mr. Doug Smith held an FCC First Class Radiotelephone license by age 16 and a General Class amateur radio license at age 12. He received a B.E.E.E. degree from Vanderbilt University in 1969 and an M.S.E.E. degree from the California Institute of Technology in 1970. In 1970, he joined AT&T Bell Laboratories as a Member of Technical Staff. He retired in 1996 as a Distinguished Member of Technical Staff. From February 1996 to April 2000 he was Manager of EMC Development and Test at Auspex Systems in Santa Clara, CA. Mr. Smith currently is an independent consultant specializing in high frequency measurements, circuit/system design and verification, switching power supply noise and specifications, EMC, and immunity to transient noise. He is a Senior Member of the IEEE and a former member of the IEEE EMC Society Board of Directors.
Dr. Ege Engin received his Ph.D from the University of Hannover, Germany. From 2005 to 2008, Dr. Engin was with the Packaging Research Center at Georgia Tech, where he was an Assistant Director of Research. Previously, he was with the Fraunhofer-Institute for Reliability and Microintegration (IZM), Berlin. Since 2008, he is an Assistant Professor in the Electrical and Computer Engineering Department of San Diego State University. He has more than 80 publications in journals and conferences in the areas of signal and power integrity modeling and simulation and three patents. He is the co-author of the book "Power Integrity Modeling and Design for Semiconductors and Systems," published by Prentice Hall in 2007. Dr. Engin is the recipient of the Semiconductor Research Corporation Inventor Recognition Award in 2009.
Registration Rates: |
Before 9/20 |
9/21 - 10/11 |
| IEEE Member | $250 | $275 |
| non-IEEE Member | $275 | $300 |
| Student/Un-Employed* | $100 | $125 |
*Full time students only with valid student ID presented on site
Group Discount: Any registration of a group of 5 or more from the same company will qualify for a rate of $250 per person. This group rate will be offered up to the October 11 deadline.
Registration:
Use either the Registration Form or
via PayPal:
NOTE: The registration fee includes one copy of the technical program, continental breakfast, lunch, refreshment breaks, and the reception at the conclusion of the event. The organizing committee reserves the right to substitute speakers, restrict size, or to cancel the event and exhibition. In the event the organizing committee cancels this event, registration fees will be fully refunded. Individuals canceling their registration prior to September 27 will receive a full refund. No refunds will be made to individuals who cancel their registration after September 27. Substitutions are allowed. Attendance is limited. Registration will be confirmed on a first come, first served basis.
For those of you traveling from out of town, you can get a discounted rate at the Biltmore Hotel & Suites Santa Clara. It will be $149.00 in a standard garden room or $156.00 in a tower suite, with wireless internet access included. You may make reservations at 800-255-9925, and refer to "IEEE SCVEMC Mini Symposium 2012" Or you can access the following link: hotel reservations
Exhibitors:
Vendor Registration:
Use either the Vendor Registration
Form or via PayPal:
Date: Tuesday, January 08, 2013
5:30pm: Networking/light dinner
6:30pm: Presentation
7:45pm: Adjourn
Light Dinner and beverages will be served for a fee. Coffee, tea, and snacks are served free of charge.
Location: TBD
Title
Differential Signaling Is the Opiate of the Masses
Speaker
Sam Connor, IBM
Abstract
A large concern with the proliferation of differential signaling is the false sense of security that comes along with its usage. Differential signals are hailed for their immunity to noise coupling and for their propagation characteristics. Differential receivers have great common mode rejection, and with equalization, receivers can pull meaningful signals out of a closed eye diagram. But with all of these benefits, the often forgotten drawback is that differential signals on PCBs are not truly differential and they do not perfectly cancel. The various asymmetries in the routing of the differential pair and the impedance discontinuities of vias and connectors and the imbalance and skew of the drivers all create a common mode signal on the differential pair that can cause serious EMC problems when coupled to other nets or radiated from cables and connectors.
Biography
Date: Tuesday, February 12, 2013
5:30pm: Networking/light dinner
6:30pm: Presentation
7:45pm: Adjourn
Light Dinner and beverages will be served for a fee. Coffee, tea, and snacks are served free of charge.
Location: TBD
Title
Micro and Nano miniaturization of systems
Speaker
Madhavan Swaminathan, Georgia Institute of Technology, Atlanta
Abstract
The main driver for the semiconductor industry has been Moore’s law where the doubling of transistors has led to phenomenal increase in functionality of the integrated circuit (IC). Today, microprocessors support a billion transistors, run at a frequency that is 250X higher than 2 decades ago and provide performance close to a super computer in a handheld device. However, integrating a System on Chip (SOC) has still not been possible due to technical and business reasons. This has led to highly integrated ICs but bulky systems. Today, the need for including sensing and energy harvesting devices for biomedical and other electronic applications is becoming necessary. These require the integration of nano-materials, nano- sensors and nano-generators into the SOP platform.