NTW Logo (Black)

About IEEE

IEEE Membership

Products and Services


IEEE Organizations


IEEE Nav Bar




Meeting and Seminar Archive:

Date:  Nov 9, 2009

Title: Digital Compensation of Dynamic Acquisition Errors at the Front-End of High-Performance A/D Converters

Speaker: Dr. Parastoo Nikaeen, Netlogic Microsystems

(This talk is based on the speaker's doctoral work at Stanford University.)


Abstract: In A/D converter applications such as wireless base stations, IF sub-sampling is an attractive method for minimizing component count and system cost. By applying this method, one or more steps of down-conversion are removed from the receiver path and some of the analog front-end signal processing functions can be moved to the digital domain. In such a solution, the ADC's linearity at high input frequencies becomes a critical issue. Despite the use of a dedicated track-and-hold amplifier (THA), nonlinearities in the circuit's input network often introduce dynamic errors that limit the performance of the ADC at high input frequencies.

In this talk, I will present a digital enhancement scheme that is specifically tailored to remove high frequency distortion caused by the dynamic nonlinearities at the sampling front-end of ADCs. The basic concept of digital compensation here is to apply the inverse nonlinear function to the digital output of the ADC in order to minimize its error over the desired frequency range. Conceptually, a nonlinear system with memory can be modeled with a Volterra series. However, the inverse Volterra series becomes very complex as the order of nonlinearity and memory in the system increases and it requires intensive computational power that is impractical even in today's fine-line technology. Our proposed algorithm uses information about sources of nonlinearities and judicious modeling to simplify the digital post processing scheme. Applying the method to a 14-bit, 155-MS/s ADC provides > 83 dB SFDR up to f_in = 470 MHz. The post-processing block is estimated to consume 52 mW and occupy 0.54 mm^2 in 90-nm CMOS.  



Parastoo Nikaeen received the B.S. degree in electrical engineering from Sharif University of Technology, Tehran, Iran, in 2001 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 2004 and 2008, respectively. Her doctoral research focused on modeling and correction of nonlinear errors in analog-to-digital converters.

During summer 2006, she was with Rambus Inc. Los Altos, CA, where she worked on design and characterization of sampler architectures at the front-end of serial communication receivers. She is currently with NetLogic Microsystem Inc, Mountain View, CA designing analog/mixed-signal integrated circuits for high-speed data communication systems.

Back to main page