Meeting and Seminar Archive: Date: October 21, Thursday, 2010 Subject: Tutorial on "Status of knowledge on non-binary LDPC decoders" Joint meeting with IEEE Solid State Circuits Society Speakers: Prof. David Declercq (ENSEA in Cergy-Pontoise) AbstractIn this tutorial, the iterative decoding techniques for non-binary LDPC codes will be presented, both from the theoretical aspects of Belief Propagation and its analysis, and from more practical aspects of efficient implementation. In a first part, the main difference between iterative BP decoding of binary and non-binary LDPC codes will be highlighted. Then, in a second part, the solutions proposed in the literature to reduce the complexity of non-binary decoders, both for memory storage and computational burden reduction, will be presented. Some directions of research and development about non-binary decoders will be discussed. Finally, the outstanding advantages of generalized non-binary decoders on clustered graphical models of several error correcting codes will be presented. Biography: David Declercq was born in June 1971. He graduated his PhD in Statistical Signal Processing 1998. He worked on a new Gaussianity test based on Hermite polynomials properties, and the characterization and the blind identification of non-linear time series. After his PhD, he oriented his researchs towards digital communications, and especially coding theory and iterative decoder design. He started to work on LDPC codes in 1999, both from the code and decoder design aspects. Since 2003, he made a major effort in studying and developping LDPC codes and decoders in high order Galois fields GF(q), with q>>2. A large part of his research projects are related to non binary LDPC codes. He mainly investigated two directions: (i) the design of GF(q) LDPC codes for short and moderate lengths, and (ii) the simplification of the iterative decoders for GF(q) LDPC codes with complexity/performance tradeoff constraints. David Declercq published more than 20 papers in major journals (IEEE-Trans. Commun., IEEE-Trans. Inf. Theo., Commun. Letters, EURASIP JWCN), and more than 70 papers in major conferences in ICT. He is currently full professor at the ENSEA in Cergy-Pontoise, France, a graduate school in Electrical Engineering. He is a member of the ETIS laboratory, general secretary of the National GRETSI association, and member of the GdR-ISIS direction team. He is currently the recipient of junior position at the "Institut Universitaire de France". Back to main page