Dynamic Heterogeneous Architectures to Address The Energy-Efficiency Crisis

Past

Dynamic Heterogeneous Architectures to Address The Energy-Efficiency Crisis The microprocessor industry is at a crossroads. While it continues to scale performance with each generation, we continue to drive this critically important technology domain. When performance scaling stops, microprocessors become a generic commodity and no longer a technology driver or enabler. Because modern processors are most heavily constrained by power, and sometimes energy, performance scaling no longer falls naturally from increased transistor counts. Instead, total performance is maximized by maximizing performance/Watt. Future computing platforms will need to be flexible, scalable, conservative on power, while saving size, weight, energy, etc. In addressing these challenges, microprocessor industry is moving towards heterogeneous architecture design. Heterogeneous designs promise to push the envelope of power efficiency further by enabling general purpose processors to achieve the efficiency of customized cores. By enabling more diverse designs, and designs that are customized dynamically, we can push the efficiency envelope even further. This talk first reviews the major challenges facing semiconductor industry; in general performance, power, temperature and reliability, and in specific dark and unreliable silicon. The talk then introduces the concept of heterogeneous architecture to address the efficiency crisis and briefly reviews the state of the art in static and dynamic heterogeneous architectures in industry and academia. The talk then presents 3D design concept and argue how it can eliminate the fundamental barrier to dynamic heterogeneity. Speaker: Houman Homayoun is an Assistant Professor of the Department of Electrical and Computer Engineering at George Mason University. He also holds a joint appointment with the Department of Computer Science. Prior to joining George Mason University, He spent two years at the University of California, San Diego, as National Science Foundation Computing Innovation (CI) Fellow awarded by the Computing Research Association (CRA) and the Computing Community Consortium (CCC). Houman research is on power-temperature and reliability-aware memory and processor design optimizations and spans the areas of computer architecture, embedded systems, circuit design, and VLSI-CAD, where he has published more than 50 technical papers on the subject. He is currently leading a number of research projects, including the design of next generation server architecture for big data computing, 3D heterogeneous multicores, big data acceleration, rare-event analytics computing, and non-volatile logic for security and thrust, funded by National Science Foundation (NSF), Defense Advanced Research Projects Agency (DARPA) and General Motors Corporation. Houman was a recipient of the four-year University of California, Irvine Computer Science Department chair fellowship. He received his PhD degree from the Department of Computer Science at the University of California, Irvine in 2010, an MS degree in computer engineering in 2005 from University of Victoria, Canada and his BS degree in electrical engineering in 2003 from Sharif University of technology.