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FPGA-Friendly High Performance Soft Processor Architectures


FPGA-Friendly High Performance Soft Processor Architectures
Cost: No Charge
Date: Tuesday, September 13, 2011
Time: 11:00
Location: ECS 660
Speaker: Kaveh Aasaraai, from the University of Toronto

Abstract: In the world of embedded computing, Field Programmable Gate Arrays, FPGAs, play a significant role. Most embedded designs utilizing FPGAs include soft processors for their low development cost and high flexibility. As embedded applications evolve, higher processing power is needed, putting pressure on the soft processor logic. Although high performance architectures have been studied for decades on ASICs, no thorough study is done on the applicability of such architectures to the programmable fabric. We redesign high performance architectures, for example out-of-order execution, and propose FPGA-friendly architectures specialized for such environments. We have proposed a novel check-pointing mechanism, register renaming, and non-blocking cache architecture which are specifically designed for FPGA implementation. Bio: Kaveh received his bachelor's degree in software engineering from Sharif University of Technology in 2005. He moved to the University of Victoria and in 2007 received his Master's degree on low-power branch prediction for high performance processors. Since 2007 he's been a PhD student at the University of Toronto working on high performance soft processor architectures.