| IEEE Xplore Digital Library | IEEE Standards | IEEE Spectrum | More Sites

GPU Architecture Challenges for Throughput Computing


GPU Architecture Challenges for Throughput Computing
Cost: No Charge
Date: Thursday, September 02, 2010
Time: 11:00
Location: EOW 430
IEEE Computer Chapter Technical Meeting,
Guest Speaker: Dr. Tor Amodt, Assistant Professor, UBC

Abstract: The use of commodity graphics processors (GPUs) for non-graphics computing applications is growing rapidly. This talk will begin with a brief introduction to GPU Computing and then describe challenges with, and proposed improvements to, branch handling, memory access scheduling, and on-chip interconnects in GPU-like manycore accelerators. The proposed hardware optimizations are aimed at increasing the variety of applications that can benefit from these architectures and/or improving hardware cost effectiveness. Bio: Tor M. Aamodt received his BASc, MASc and PhD degrees at the University of Toronto. He is an assistant professor in the ECE department at UBC. His research focuses on computer architecture including manycore accelerators (GPUs) and analytical performance modeling of processor architectures. Prior to joining UBC he worked at NVIDIA on the GeForce 8 Series GPU (G80) and interned at Intel's Microarchitecture Research Lab. He has three US patents related to computer architecture.