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On Energy Effective Graphene Based Boolean Gates


On Energy Effective Graphene Based Boolean Gates
Cost: No Charge
Date: Thursday, October 18, 2018
Time: 13:30
Location: ECS 660
Dr Sorin Cotofana

Abstract In this presentation we argue and provide Non-Equilibrium Green’s Function Landauer formalism-based simulation evidence that in spite of Graphene’s bandgap absence, Graphene Nanoribbons (GNRs) can provide support for energy effective computing. We start by demonstrating that: (i) band gap can be opened by means of GNR topology and (ii) GNR’s behaviour can be controlled according to some desired functionality via top/back gate contacts. Afterwards, we introduce a generic GNR based Boolean gate structure, composed of a pull-up GNR performing the gate Boolean function and a pull-down GNR performing the gate inverted Boolean function. Subsequently, by properly adjusting GNRs' dimensions and topology, we design 2-input Graphene based Boolean gates (AND, NAND, and XOR), inverter, and buffer. Our SPICE simulations indicate that the proposed gates exhibit a smaller propagation delay, from 23% for the XOR gate to 6x for the AND gate, and 2 orders of magnitude smaller power consumption, when compared with 7nm CMOS based counterparts, while requiring 1 to 2 orders of magnitude smaller active area footprint. These results clearly indicate that GNR-based gates have great potential as basic building blocks for future beyond CMOS energy effective nanoscale circuits. Bio Sorin Cotofana (M'93-SM'00-F'17) received the M.Sc. degree in Computer Science from the 'Politechnica' University of Bucharest, Romania, and the Ph.D. degree in Electrical Engineering from Delft University of Technology, The Netherlands. He is currently an Associate Professor with the Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, the Netherlands. His current research is focused on: (i) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components; (ii) ageing assessment/prediction and lifetime reliability aware resource management; and (iii) unconventional computation paradigms and computation with emerging nano-devices. He (co-)authored more than 250 papers in peer-reviewed international journal and conferences, and received 12 international conferences best paper awards, e.g., 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, 2001 International Conference on Computer Design. He served as Associate editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015), and IEEE Nano Council CASS representative (2013-2014) and has been actively involved in the organization of many international conferences. He is currently Associate Editor in Chief and Senior Editor for IEEE Transactions on Nanotechnology and Steering Committee member for IEEE Transactions on Multi-Scale Computing Systems. He is a Fellow IEEE member (Circuits and System Society (CASS) and Computer Society) and a HiPEAC member.