Wednesday, April 18, 2007
IEEE Circuits and Systems, Dallas Chapter:   Seminar
 
https://ewh.ieee.org/soc/cas/dallas/ 
 

Title : A 65nm C64x+^TM Multi-Core DSP Platform for Communication Infrastructure

Presenter :  Raguram Damodaran, Senior Member Technical Staff, Texas Instruments Inc., Dallas, TX

Date : Wednesday April 18, 2007. 6:30pm, Refreshments - Pizza & Drinks ; 7:00pm, Program

Location : Dallas Texins Activities Center, Conf Room 1 (North end of  Texas Instruments expressway site, 13900 N Central Expw.; site  entrance on north-bound access road, between Midpark Rd. & Spring Valley Rd.)

Abstract:

A Single-Chip WCDMA Baseband Processor is industry's most highly integrated digital signal processor (DSP) targeted toward Wideband Code Division Multiple Access (W-CDMA) base stations. This  three-core DSP, running at 1GHz per core, supports all of the necessary baseband functions required for a macro base station – on a single chip. Designed specifically to solve problems at a system level, this "baseband on a chip" eliminates the need for FPGAs, ASICs and other bridging devices, reducing the total bill of materials for OEMs by up to a factor of five, resulting in lowered equipment costs for service providers. It is based on C64x+™ DSP core and implemented in leading edge 65 nm 7 LM CMOS process. The 300M transistor IC can perform up to 24000MIPS, 8000 16b MMACs per second, coupled with symbol-rate and chip-rate acceleration and dissipates less than 6W. The TCI6488 DSP is  an ideal solution for pico, micro and macro BTS and enables an SOC baseband solution for WCDMA Tx and Rx applications.

Brief Biography

Raguram Damodaran received his B.Engg from Coimbatore Institute of Technology, India in 1991 and his MSEE from Texas A&M University, College Station in 1993. He has been with Texas Instruments (TI), Dallas, TX since 1993. He is Senior Member Technical Staff at TI.  He leads the configurable C64x dsp cores design team in DSPS. He also leads the WW Clock teams in ASP and is  the design lead and architect of the TI's  programmable memory testing (pBIST) architecture..