Thursday, March 16, 2006
IEEE Circuits and Systems, Dallas Chapter:   Seminar

https://ewh.ieee.org/soc/cas/dallas/ 
 

IEEE Circuits and Systems, Dallas Chapter: Seminar

Title: TI DM642 DSP optimization techniques for real time video application

Presenter: Dr. Jagadeesh Sankaran, Texas Instruments Incorporated, Dallas, TX

Date: Thursday March 16, 2006. 6:30pm, Refreshments; 7:00pm, Program

Location: Dallas Texins Activities Center, Conf Room 1 (North end of Texas Instruments expressway site, 13900 N Central Expw.; site entrance on north-bound access road, between Midpark Rd. & Spring Valley Rd.)

Abstract :

DSP architectures have evolved over the years to incorporate many advanced features to cope with the needs for increased processing. Large applications are being deployed on programmable architectures are dependent on a combination of architecture, optimization and software written on these architectures. This talk will review several examples that pertain to video and image processing and present optimal mappings to the DM642 architecture. It will discuss techniques for developing optimal software from a performance perspective.

A precise definition of optimality for a given architecture will be developed and the benefits and features of programmable DSP architectures in this space will be discussed. The flexibility that software based video codecs can offer will be illustrated using an actual product to show that DSP based architectures are uniquely positioned to drive flexible and creative products in the consumer market..

Biography :

Dr. Jagadeesh Sankaran was born in Chennai India. He acquired a Bachelor's Degree in Electronics and Communication Systems from the National Institute Of Technology, Warangal, India in 1995. He finished his master's degree in electrical engineering, from the Louisiana State University, Baton Rouge in 1998. He joined Texas Instruments DSP group in 1998 as DSP software applications engineer. His focus has been on architecture definition, instruction set and memory benchmarking. He played a key role in the definition of C6211, C64x, DM642 DSP architectures. He serves as a technical lead for the video team in mapping video encoder and decoder algorithms to TI DSP architectures. He has three granted patents by the USPTO, in areas of Reed Solomon and Context based arithmetic encoding/decoding (CABAC)and five pending applications. He finished his Ph.D degree from University of Texas at Dallas in 2003, which had a focus on media architectures for wavelet based video coding.

He was elected as Member of the Group of Technical Staff in 2003. He has authored over 12 papers in various conferences. His research interests include motion-compensated wavelets, texture analysis and scalable video coding with complexity reduction.

Sudhind Dhamankar, Publicity Chair, IEEE CAS/Dallas, 214-567-8914