Date: Tuesday, January 25, 2000
Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1 and 2
Complimentary Dinner 6:30PM, 7:00PM Program.
A Low Voltage Low Noise Differential Feedback Amplifier
Program Summary:
Many fully integrated receivers for digital and analog radio communications
use a low noise amplifier (LNA) for the input stage in order to increase
the
system sensitivity. Thus, often the LNA represents the interface between
the
system on silicon and the external circuitry (antenna, filters etc.)
working
at high frequency rate. In the RF field the standard blocks have 50 ohm as
input and/or output impedance. Since on silicon the signal path lengths are
negligible compared with the wavelength, fully integrated receivers
requires
only 50 ohm input impedance, while the LNA output is directly fed into the
mixer.
High gain and low noise specifications in LNAs do not trade with a good
return loss. This causes the use of an external matching network that
increases cost and complexity of the application circuit.
This seminar presents an innovative low noise differential amplifier with
an
intrinsic low input impedance, good noise figure and high gain. It is also
capable to work with a supply voltages as low as 2 V.
Guglielmo Sirna was born in Palermo, Italy, in 1968. He graduated in 1993
with a "Laurea" degree (M.E.E.) in electronics engineering from the
University of
Palermo.
From 1993 to 1995 he was in charge of the CAD-Microwave Labs of the Center
for Electronic Research in Sicily (CRES) and worked on GaAs MESFET
modeling.
From 1995 to 1998, he was with STMicroelectronic-RF Design Group. He
designed a fully integrated GPS receiver and several circuits for mobile
communication system using high-speed bipolar technology.
In 1998 he joined the Texas Instrument Inc. RF Wireless Design Group in
Dallas, TX. He is currently working on fully integrated transceivers for
mobile communication.
For a copy of the trasparencies (US Patent pending on some of the
material) click here (almost 1.2MB).
For any further information please contact:
Guglielmo Sirna
Texas Instruments Inc.
P.O.Box 660199, MS 8729
Dallas, TX 75243
email:g-sirna1@ti.com
Date: Tuesday, February 22, 2000
Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 4
Complimentary Dinner 6:30PM, 7:00PM Program.
A statistical design methodology for yield enhancement of Low Voltage
Analog VLSI Circuits
Program Summary:
Due to inherent fluctuations in any integrated circuit manufacturing
process, the functional yield is always less than 100%. As the complexity
of VLSI chips increase, and the dimensions of VLSI devices decrease, the
sensitivity of performance to process fluctuations increases, thus further
reducing the functional yield. Moreover, with current trends of higher
levels of integration leading to complete mixed-signal systems on a chip,
yield loss due to the analog component must be minimized such that it has
little effect on the yield of the mixed-signal chip. The need for the
robust design of low voltage low power CMOS analog VLSI circuits is
tremendously growing. To produce cost effective, manufacturable analog and
mixed-signal chips, circuit designers must work to enhance the functional
yield. Statistical techniques which account for random intra-die
variations and process parameter correlations must be used to achieve this
goal. This is even more critical for low voltage designs, as random
variations do not scale down with feature size and supply voltage.
A robust design methodology is introduced in this presentation, which
consists of the statistical MOS (SMOS) model to include the random process
variations into the simulation environment, and statistical techniques
such as Design of Experiments (DOE) and Response Surface Methodology
(RSM), to determine the most important transistors for the circuit
performance and the optimum size for these transistors. The methodology
will be applied to a low voltage (<3V) circuit example.
Tuna B. Tarim received her B.Sc., M.Sc. and Ph.D. degrees in Electronics
Engineering from Istanbul Technical University, Turkey in 1992, 1994 and
2000, respectively. She is currently with Texas Instruments, Mixed-Signal
Wireless group, working on the statistical modeling and design of analog
VLSI circuits. Her research interests include functional yield
enhancement, statistical design and optimization of analog and
mixed-signal VLSI circuits, and CAD of VLSI circuits.
For a copy of the trasparencies click here and here
(almost 300K)
For any further information please contact:
Dr.T.B.Tarim
Texas Instruments Inc.
P.O.Box 660199, MS 8729
Dallas, TX 75243
email:tuna@ti.com
|
|
IEEE Dallas CAS Workshop on Low-Power & Low Voltage
Circuits & Systems
Monday, 27th March 2000
Harvey Hotel, Plano, Texas
Information on this successful past event can be found
|
Date: Thursday, May 25, 2000
Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1 and 2
Complimentary Dinner 6:30PM, 7:00PM Program.
Floating Body Effects in Partially Depleted SOI
Program Summary:
Silicon-On-Insulator (SOI) is projected to increase circuit performance by 5% to 25% or more.
The wide range of this projection is due in part to varying interpretations of the impact of floating
body effects on circuit performance. The ultimate future for partially depleted SOI will depend on
the success of circuit designers to deal with and take advantage of these floating body effects.
This talk will cover the basics of SOI and explain floating body effects in terms of physical
understanding and circuit design. The variation of gate delay based on previous switching history
will be explained. Circuits using body ties to enhance performance will also be presented.
Dr. Houston received the BS in Physics from the Polytechnic Institute of Brooklyn and the MS
and PhD in Physics from the University of Pennsylvania where he held an NSF Fellowship. He has
held a variety of positions at Texas Instruments where he is currently a Distinguished Member of
Technical Staff with responsibility for SRAM cell development and SOI circuit design. He is a
Senior Member of the IEEE and was general chair of the 1999 IEEE International SOI Conference.
For a copy of the trasparencies click here
(almost 150K)
For any further information please contact:
Dr.T.Houston
Texas Instruments Inc.
P.O.Box 650311
Dallas, TX 75243
email:ted-houston@ti.com
Date: Wednesday, August 2, 2000
Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1 and 2
Complimentary Dinner 6:30PM, 7:00PM Program.
Low-voltage analog CMOS circuits based on floating voltage sources
Program Summary:
Technolgy as well as power dissipation considerations have lead to a
continuous reduction of the supply voltages of CMOS circuits. Supply
voltages are expected to fall below 1V within the next few years .
Most conventional analog circuits have very poor performance
characteristics or are not functional at all in a reduced supply
environment. Recently and in order to overvcome this limitation some
new
architectures have been introduced. In this presentation a family of
high performance low-voltage analog CMOS circuits that operate with a
single supply voltage close to a transistor's threshold voltage and
with
wide input and output signal ranges are discusssed. These circuits are
based on the utilization of static and dynamic floating voltage sources
in combination with circuits denoted "flipped voltage followers".
Examples of some low-voltage circuits discussed in this presentation
include: class AB operational amplifiers, linear transconductors, four
quadrant analog multipliers, current mirrors, high frequency filters,
precision rectifiers, etc.
Jaime Ramírez-Angulo is currently Professor of Electrical Engineering,
IEEE Fellow and Director of the VLSI lab at the Klipsch School of
Electrical and Computer Engineering, New Mexico State University in Las
Cruces, New Mexico, USA. He received a degree in Communications and
Electronic Engineering (Professional degree), a M.S.E.E. from the National
Polytechnic Institute in Mexico City and a Dr.-Ing degree form the
University of Stuttgart in Stuttgart, Germany in 1974, 1976 and 1982
respectively. His research is related to various aspects of analog and
mixed-mode VLSI and includes currently following fields: low-voltage
CMOS circuit design, test techniques for mixed-mode VLSI systems, analog
fuzzy processors and analog arrays for image processing.
The contents of the talk are reported in the following publications:
- "A CMOS op-amps for a single supply close to a threshold voltage and
with
almost rail-to-rail signal swing", J. Ramírez-Angulo, A Torralba, R.G.
Carvajal and J.Tombs 1999 IEEE International Symposium on Circuits and
Systems, Orlando Fl, May 30-June 2, 99, pp. II-408-411.
- Two new VHF tunable CMOS Low-Voltage Linear Transconductor and its
Application to HF gm-C filter Design," F. Munoz, A. Torralba, J. Toms,
and J. Ramírez-Angulo, IEEE International Symposium on Circuits and
Systems (ISCAS) 2000, May 28-31, Geneve, Switzerland
- "Floating Gate Based Tunable Low-Voltage Linear Transconductor and its
application to HF,". Munoz, A. Torralba, J. Toms, and J.
Ramírez-Angulo,
IEEE International Symposium on Circuits and Systems (ISCAS) 2000, May
28-31, Geneve, Switzerland.
- "High Speed High Precision Voltage Mode MIN/MAX Circuits in CMOS
Technology, " R.G. Carvajal, J. Ramírez-Angulo and J. Tombs, IEEE
International Symposium on Circuits and Systems (ISCAS) 2000 , May
28-31, Geneve, Switzerland.
- A 1.5V linear transconductor with wide bandwidth ands wide input and
output signal swings," J. Ramírez-Angulo, R.G. Carvajal, A. Torralba
and j. Martinez-Heredia, IEEE International Symposium on Circuits and
Systems (ISCAS) 2000, May 28-31, Geneve, Switzerland
- "A Fully Parallel CMOS Analog Median Filter, " A. Diaz-Sánchez, J.
Ramírez-Angulo, A. Lopez and E. Sánchez-Sinencio,? IEEE International
Symposium on Circuits and Systems (ISCAS) 2000, May 28-31, Geneve,
Switzerland
- "1.4V Supply, wide swing, high frequency CMOS Analogue multiplier with
high current efficiency," J. Ramírez-Angulo, R.G. Carvajal, and . J.
Martinez-Heredia, IEEE International Symposium on Circuits and Systems
(ISCAS) 2000, May 28-31, Geneve, Switzerland
- Very Low-Voltage Class AB CMOS and Bipolar Precision Current
rectifiers," J. Ramírez-Angulo,? R.G. Carvajal, J. Tombs and A.
Torralba, IEEE International Symposium on Circuits and Systems (ISCAS)
2000, May 28-31, Geneve, Switzerland
- Low-voltage CMOS amplifiers with wide input-output swing based on a
novel scheme," J. Ramírez-Angulo, A Torralba, R.G. Carvajal and
J.Tombs,
IEEE Transactions on Circuits and Systems-I, vol. 47, No. 5, May 2000,
pp. 772-774.
Date: Tuesday, Nov 14, 2000
Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1 and 2
Complimentary Dinner 6:30PM, 7:00PM Program.
Opamp Compensation for Low-Voltage, Mixed-Signal Designs
Program Summary:
As power supply voltages are reduced, trends in opamp
designs for mixed-signal systems are towards multiple non-cascode stages.
This tutorial will cover frequency compensation techniques applicable to
three and four stage amplifiers. After a review of basic pole-splitting,
the newly published Nested Miller and Nested Gm-C compensation schemes
will be described.
John W. Fattaruso received his B.S., M.S. and Ph.D. degrees at the
University of California at Berkeley through 1986. Since then he has
worked on MOS analog VLSI technology development with Texas Instruments
corporate research. He has also served as a consultant to Seeq
Technology
and as an instructor at UC Berkeley. His research interests include
analog and RF circuit design, circuit simulation and optimization, neural
networks and numerical analysis. He currently holds 11 patents in
circuit
design, and has authored or co-authored 16 journal and conference papers.
He has recently served on the analog program subcommittee of the ISSCC
and
as guest editor of the JSSC.
For a copy of the trasparencies click here
(almost 900K)
For any further information please contact:
Dr.J.Fattaruso
Texas Instruments Inc.
P.O.Box 660199
Dallas, TX 75243
email:johnf@ti.com
