Leakage mechanisms and leakage power reduction in nanometer digital logic and memory designs

Presenter: Prof Ramalingam Sridhar, Department of Computer Science and Engineering, University at Buffalo
Date : December6, 2004 Monday

Location:
Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1
6:30pm, light dinner and refreshments; 7:00pm, program.

Abstract:
As we move towards the nanometer regime, scaling of both the supply and threshold voltages of transistors enables high-speed and low-power operation. However, it causes a significant increase in the leakagecurrent due to its exponential relation with the threshold voltage. Different leakage currents coupled with the unpredictable variations in the process parameters is a major concern for designers. Consequently, the circuit designers need to work hand in hand with the device engineers to deliver high-performance yet low-power and robust systems. This talk will consider the different leakage mechanisms in nanometer scale devices, challenges faced by the designers, and discuss in detail different device architecture and circuit/CAD techniques for leakage power reduction for logic and memoriy circuits. We will also present some of our recent efforts towards leakage reduction and results.

Biography:
Professor Ramalingam Sridhar is with the Department of Computer Science & Engineering at University of Buffalo, (SUNY). His research interests are in Deep submicron VLSI Design, Wave Pipelining, Clocking and Synchronization, Low power DSP and memories, high level power minimization and wireless, secure, embedded system designs. He got his Ph.D. in Electrical and Computer Engineering from Washington State University, Pullman, Washington in 1987. He was the Chair of the CAS Technical committee on VLSI Systems and Applications from 2000-2002. Heserved on the editorial board of IEEE Transactions on Circuits and Systems I, II and IEEE Transactions on VLSI and the Journal of Circuit, Systems and Computers, and is currently an editor for IEEE Circuits & Devices magazine. He has served as the General Chair of ASIC/SoC Conference in 1999 and has served in committees of numerous conferences in varying capacities. Dr. Sridhar has several patents and publications in his research areas. He was selected as the Teacher of the Year in Engineering by Tau Beta Pi(1991-92) Engineering honor society.

SoC Design and It’s Challenges

Presenter:  Atul Jain, Texas  Instruments
Date : 16 Novemner 2004, Tuesday
 
Location:
 Dallas Texins Association at Texas Instruments
 13900 N Central Expwy.  (north-bound access road between Midpark Rd. & Spring Valley Rd.)
 Conference Room 6 (second floor)
 6:30pm, Officer elections and light dinner and refreshments; 7:00pm, program.
 
Abstract
Today’s deep submicron semiconductor technology has enabled large scale integration of multi-million gates into a single chip, called System-On-a-Chip (SoC).  All these systems require integration of multiple standard of-the-shelf components and/or custom chips that include RISC processor and/or DSP cores along with memory, peripherals, bus bridges, and user defined logic. This integration has resulted in several challenges for the design teams, in terms of increased design complexity, functional verification, timing closure, physical design, signal integrity, reliability, manufacturing test, and package design. Another critical parameter that hugely impacts SoC design cycle time and productivity is “change”. Coping with the challenges of concurrently developing specifications, IP and design constraints, to name a few, become an imperative. This necessitates some changes into a typical SoC development process.
This talk will review different design methodologies that are followed in the industry to design SoCs.  Focus will be on design management and planning which is an important ingredient to meet the time-to-market demands.

Biography:
Atul Jain has Ph.D. (1994), M.Sc. (1986), and B.E. (1984). His Ph.D. work was in the area of “Multiple-Valued Logic (MVL) Design in Current-mode CMOS”.  He proposed a functionally complete multiple-valued logic set of operators and developed software that can be used to implement MVL designs using the proposed set of operators.  He received university graduate research scholarship for both M.Sc. and Ph.D. studies.
In 1996, he joined Texas Instruments Inc., Dallas where he is Managing SoC designs in broadband applications and is a Member Group of Technical Staff.  He has successfully managed SoC designs in the area of fixed wireless access, voice over packet (VoP), communications processors, and DSL CPE modems.  He has been involved in defining methodology for design reuse.  Before joining TI, he has worked as Systems Engineer with Canadian Microelectronics Corporation (CMC), Kingston, Canada (1995-1996) where he was a key member of the team that defined design methodologies for rapid prototyping for digital chips.  He has also been a Visiting Researcher, under international visiting researcher program, for a year at Central Research Laboratory, Hitachi Ltd., Tokyo, Japan (1987-88). 
His research interest includes SoC design methodology, design automation, binary and multiple-valued logic VLSI design, design for test (DFT). He has published several journal and conference papers in the area of binary and multiple-valued logic VLSI design. He has organized and presented a half day tutorial on "SoC Design Methodology" at IEEE SoC Conference, Sep. 2004 at Santa Clara, California and two full day hands-on tutorials on "Rapid-prototyping of Digital Designs" at IEEE sponsored conferences in Canada. He has also taught several engineering courses at university and technical college levels.



Digital Radio Processor Alternative to Conventional RF

Presenter: Dr. Robert Bogdan Staszewski, Texas Instruments
Date: 19 October 2004, Tuesday
Location: Dallas Texins Association at Texas Instruments
13900 N Central Expwy. (north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 4
Abstract:
The use of deep-submicron CMOS processes allows for an unprecedented degree of scaling in digital circuitry, but complicates implementation and integration of traditional RF circuits. The explosiv e growth of cellular radios (over half-a-billon handsets sold last year) makes it imperative to fi nd digital architectural solutions to these integration problems. In this talk, we describe a journey that started at the end of 1999 with a mission to find digital replacements of traditional RF circuits, which are difficult to design, manufacture, characterize and test, and require a truly unique set of skills. At that time, the digital gate density of a l eading edge 130 nm CMOS was approaching 150 kgates per mm2 with the demonstrated speeds of 750--10 00 MHz for disk drive read channels with which the author was previously involved. The RF circuits , on the other hand, do not scale well with the CMOS process advancements and are relatively large with passive components taking a larger fraction of mm2. It did not take long to realize high cost of RF components in signal processing currency ? tens of thousands of digital gates! ? and start experimenting with direct ways of synthesizing GHz RF sig nals using high-speed high-density digital logic. The journey has led to a first ever demonstratio n of a functional multi-GHz digital RF transmitter integrated into a DSP processor. The RF transmi tter occupies only 0.54 mm2 (fraction of a dollar in incremental cost) and is built from the groun d up using digital techniques. The TX is based on an all-digital phase-locked loop (ADPLL) with a wideband direct frequency modulation capability. Due to its programmability, flexibility and porta bility, the digital RF transmitter and frequency synthesizer serve as a foundation of a Digital Ra dio Processor (DRP). The presented ideas have resulted in a commercial single-chip Bluetooth radio and are instrumental for a single-chip GSM radio phone call that TI has officially committed unti l the end of 2004.

Biography:
Robert Bogdan Staszewski received the BSEE (summa cum laude), MSEE and PhD degrees from the Univer sity of Texas at Dallas in 1991, 1992 and 2002, respectively. From 1991 to 1995, he was with Alcat el Network Systems in Richardson, TX, working on Sonnet cross-connect systems for fiber optics com munications. He joined Texas Instruments in Dallas, TX, in 1995 where he is currently a Senior Mem ber of Technical Staff. Between 1995 and 1999, he has been engaged in advanced CMOS read channel d evelopment for hard disk drives. In 1999, he co-started a Digital Radio Processor (DRP) group with in Texas Instruments with a mission to invent new digitally-intensive approaches to traditional RF functions for integrated radios in deep-submicron CMOS processes. Dr. Staszewski is currently a d esign team leader for transmitters and frequency synthesizers in mobile wireless terminals. He has authored and coauthored over 25 papers and holds 20 issued US patents. His research interests inc lude deep-submicron CMOS architectures and circuits for frequency synthesizers, transmitters and r eceivers.

Digital Still Camera Imagepipe: Color Filter Array, Auto-focus

Prof. Nasser Kehtarnavaz, University of Texas at Dallas
Date: 25 May 2004, Monday

Location: University of Texas at Dallas, Richardson TX
Galaxy room (SU 2.602) in the Student Union.
6:30pm, light dinner and refreshments; 7:00pm, program.

Abstract:
The market for digital still cameras (DSCs) has experienced rapid growth in recent years, with sales already passing those of film cameras in 2003 and projected sales of over 51M units by 2007. In this talk, an overview of the digital camera system (DSC) is followed by a discussion on two of its specific components. These components include: (a) a color filter array (CFA) interpolation algorithm based on directional derivatives and color correlations, and (b) an auto focusing (AF) algorithm based on a rule-based search approach. The main advantage of the developed CFA algorithm is that it requires no user-defined parameter as is the case in many edge adaptive CFA algorithms. The main advantage of the developed AF algorithm is that it achieves faster focusing speeds without sacrificing focusing accuracy. These algorithms are compared with standard algorithms commonly used in digital cameras in terms of performance and speed.

Biography:
Dr. Nasser Kehtarnavaz received his PhD in electrical and computer engineering from Rice University in 1987. He is a Professor of Electrical Engineering at UTD. Previously, he was a Professor of Electrical Engineering at Texas A&M University. His research areas include signal/image processing, real-time imaging, DSP-based system design, biomedical image analysis and pattern recognition. He has authored or co-authored three books and more than 120 journal and conference papers in these areas. He is currently serving as the Editor-in-Chief of Journal of Real-Time Imaging and Chair of the Dallas Chapter of the IEEE Signal Processing Society. Dr. Kehtarnavaz is a Fellow of SPIE and a registered Professional Engineer in Texas.  

Chameleon: A Dual-Mode Bluetooth/802.11b Receiver

Dr. Edgar Sanchez-Sinencio, Texas A&M University
Date: 23 March 2004, Monday

Location: Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1 and 2
6:30pm, light dinner and refreshments; 7:00pm, program.

Abstract:
Bluetooth and 802.11b (Wi-Fi) are the leading technologies for wireless personal area networks (WPAN) and wireless local area networks (WLAN) respectively. A fully-integrated (from the LNA to the ADC) receiver capable to support both standards has been implemented in BiCMOS 0.25mm technology. A single direct-conversion architecture is employed to attain a high level of integration and low power consumption. The RF front-end (LNA, Mixer and Local Oscillator) is shared while all the baseband blocks (Channel selection filter, VGA and ADC) can be programmed to accommodate each standard. The LNA is an inductive-degenerated differential structure and the mixer is a standard Gilbert cell. The local signal (LO) generator is implemented by an integer-N type frequency synthesizer, which covers the specified band of both standards (from 2.4GHz to 2.5GHz). The VCO itself is operated at twice the LO frequency (that is from 4.8GHz to 5GHZ). The programmable low-pass channel selection filter is an OTA-C, 5th-order, Butterworth structure. It has a cut-off frequency of 600KHz/6MHz in the Bluetooth/Wi-Fi modes respectively. Dual-mode operation is achieved by switching the source-degeneration resistors of the implemented BiCMOS OTA. The VGA uses the OpAmp-R technique and RC high-pass filters are used in between the stages to reject DC offsets and prevent saturation. In Wi-Fi mode the VGA operates with 3 stages to provide a gain range of 62dB in steps of 2dB. In Bluetooth mode, a single stage is used to provide a gain step of 24dB. A configurable time-interleaved pipeline ADC digitizes the baseband signal according to the requirements of each standard (11bits at 11Ms/sec for Bluetooth and 8 bits at 44Ms/sec for Wi-Fi). The receiver achieves a sensitivity of -91dBm/-86dBm while drawing a total current of 41.3mA/45.6mA from a 2.5V supply in Bluetooth/Wi-Fi mode respectively. The measured IIP3 in both modes is -13dBm and the total chip area including pads is 19mm2. This project involved six Ph. D students and it took about 1 ½ years from concept to testing and characterization

Biography:
Dr. Sanchez received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Champaign-Urbana, in 1966, 1970, and 1973, respectively In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979-1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985-1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). He is a former President of the IEEE Circuits and Systems Technical Committee on Neural Systems and Applications and CAS Technical Committee on Analog Signal Processing. He received the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He is currently the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000-2002). He is also presently a member of the IEEE Solid-State Circuits Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member.
E-mail: sanchez@ee.tamu.edu  

Clock Distribution and Balancing for Large and Complex ASIC Designs

Speaker: Dr. Kaijian Shi, Synopsys, Inc
Date: 27 January 2004, Monday

Location: Dallas Texins Association at Texas Instruments 13900 N Central Expwy.
(north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1 and 2
Complimentary Dinner 6:30PM, 7:00PM Program.
Abstract:
Clock distribution and balancing are critically important in high performance and low power ASIC designs. Challenges come from the tight clock skew budgt and  complex clock structure that consists of multi-level clock gating, clock dividing and mode switching logic. Manual clock tree genreation that is commonly adopted in MPU designs is not applicable to ASIC designs due to time-to-market pressure and usually high clocking power consumption. Commercial clock tree synthesis tools such as Astro Clock Tree Synthesis (CTS) can generate quality clock trees in an automated process. However, the tools do not guarantee clock tree quality when the clock structure is complex and intensive clock gating logic and/or multiple modes switching logic are in the  clock distribution.

The talk is organized in two parts. In the first part, we shall have an overview of clock structures that are commonly used in chip designs and the clock distribution and balancing algorithms that form the engines in clock tree synthesis tools. In the second part, we shall look at clock distribution and balancing from an engineering point of view. We shall discuss challenges and issues involved in the clock distribution and balancing of a complex clock structure in a large high performance low power ASIC, and provide practical solutions to the issues. We shall focus the discussions on five critical areas. These areas are clock phase delay reduction, clock skew reduction, clock duty cycle distortion reduction, clock gating efficiency and clock balancing automation strategy.

Biography:
Kaijian Shi is a Principal Consultant with Synopsys Professional Services. He has 20 years experience in EDA and ASIC design, specialzing in RTL-to-GDSII timing closure  and STA of  high performane and complex ASIC designs.  For the last five years, he has been consulting on a number of projects in Texas  Instruments, Inc. where he has successfully accomplished timing closure of 8 leading edge ASIC designs.
Dr. Shi  received his B.Sc (Physics), M.Sc.(CS), M.Phil. (EE) and Ph.D. (EE) degrees in 1980, 1984, 1990 and 1994 respectively.  He has published 9 journal papers and 23  international conference papers. Dr. Shi serves as Chair of IEEE Circuits and Systems Society Dallas Chapter, member of Technical Program Committee of IEC DesignCon and SNUG, and paper reviewer of IEEE/ACM Design Automation Conference.