Note: Seminars are open to all interested parties (there is no requirement to be an IEEE member). No reservation or registration required. Dinner is on a first-come first-served basis.


Circuits and Systems, Dallas Chapter Seminar, 31 January 2005, Monday
6:30pm: Light refreshments; 7:00pm: program

Title :  "Flying-adder" frequency & phase synthesis architecture
Presenter: Liming XIU , Texas Instruments

Location: Dallas Texins Association at Texas Instruments
13900 N Central Expwy. (north-bound access road between Midpark Rd. & Spring Valley Rd.)
Conference Room 1&2

Abstract:
A frequency and phase synthesis architecture has been developed within TI in the past several years. It is commonly called
"flying-adder" architecture.  This architecture is a frequency synthesis technique that is based on PLL. The output frequency is inversely proportional to the size of frequency digital control word. It can be useful in applications that need a stable and easilycontrolled clock source. It is especially useful for application which needs a clock source of MANY frequencies. Since the invention of this architecture, it has been utilized in many products and a series of five papers have been published in IEEE journals. Due to the nature of this technique, it is likely that many other designs might also benefit from it.

The following four papers are available from IEEE Xplore:

1. Journal of Solid-State Circuits, June 2000, "An Architecture of High-Performance Frequency and Phase Synthesis".
2. IEEE Transaction on VLSI System, Oct. 2002, "A Flying-Adder Architecture of Frequency and Phase Synthesis with Scalability".
3. IEEE Transaction on Circuit And System II, March 2003, "A New Frequency Synthesis Method Based on Flying-Adder Architecture".
4. Journal of Solid-State Circuits, March 2004, "A Novel All Digital Phase Lock Loop with Software Adaptive Filter".

The first paper presents the foundation and the principle circuitry of this architecture. The second paper improves the architecture greatly in circuit level. The third paper presents an idea of overcoming the inherent jitter problem of the architecture. In system-level, this paper proposes a new frequency synthesis method that is directly comparable to fractional-N PLL.  This paper also solved a tough mathematical problem that is related to frequency accuracy. (If you are interested in this math problem and willing to provide better solution, please see the attachment) The fourth paper demonstrated an exemplary All Digital Phase Lock Loop by using this architecture as its DCO, or Digital Control Oscillator. A fifth paper, "A Flying-Adder Frequency Synthesis Architecture of Reducing VCO Stages", will be published in IEEE Transaction on VLSI System in Feb. 2005. This paper presents a technique of reducing the number of VCO stages without sacrificing the available synthesizable frequencies.

This presentation is the summary of the above five papers.

Biography:
Liming XIU graduated from TsingHua University, Beijing, China with B.S. and M.S. degrees in applied physics, in 1986 and 1988 respectively. He received his MSEE degree from Texas A&M University in 1995. He is currently a senior design engineer of Texas Instruments Inc, Member of Technical Stuff.  He has been worked on various areas of VLSI design during his TI career, such as transistor-level mixed signal design, digital front-end design and VLSI back-end integration. He has strong knowledge on all the areas of currently IC design aspects, has deep understanding on all the challenges in today's SoC integration. He is the key inventor of "flying-adder" frequency and phase synthesis architecture which has been used in many TI products. During his TI career, he has published five IEEE journal papers, several conference papers. He has one granted, five pending US patents. He is IEEE senior member. Currently, he severs as IEEE CAS Dallas chapter vice chair.