2002 IEEE Systems Packaging Japan Workshop
The 2002 IEEE Systems Packaging Japan Workshop was held February 4-6 at the NTT Musashino R&D Center just west of Tokyo. Despite the poor economic conditions, the workshop was highly successful, with 86 professionals in attendance. The workshop was held in English for the benefit of all foreign visitors. Following are just a few highlights of this informative workshop.
The workshop began with keynote speaker Hisao Kasuga of NEC discussing packaging technology in the future, particularly the JISSO roadmap. JISSO is the Japanese acronym for a total solution for interconnecting, assembling, packaging, mounting, and integrating system design. The roadmap projects extensive development of stacked 3-D structures, both with ICs on flex as well as ICs stacked directly, sometimes with through vias. Many of the same arguments heard in the US for SiP (system in package) v. SoC (system on chip) were presented.
The High Performance Systems Packaging session is always a highlight of these workshops, and this was no exception. Hubert Harrer, of IBM Böblingen, described the packaging of the Z Series 900. The large MCM supports 35 chips and handles 1300W. For the first time there was a direct comparison between an IBM-produced module, with 101 glass ceramic and 6 thin film layers, with a Hitachi-produced module, with 84 glass ceramic layers. Hitachi was able to eliminate thin film and save ceramic layers because of finer design rules (297 micron pitch v. 396.)
Erich Klink, also of IBM, described the packaging for IBM's Unix servers. This MCM is much simpler, but still requires 71 glass ceramic layers to support 4 ICs, each with over 7000 C4 bumps. The module has 5200 I/O, and 4 modules are used in a 32-way system.
Kazuhiko Umezawa of NEC described the hardware in the iPX7800 server. Their MCM contains 4 processors, control, and L2 cache. ICs are in .15 µm CMOS. Processors contain 38M transistors and run at 420 MHz. The MCM has 20 ceramic layers for power, and 8 layers of thin film wiring (4 signal layers.) Gold wiring and polyimide dielectric layers are used. Signals from board to board also run at the 420 MHz clock frequency.
In the session on Packaging for High Frequency and Wireless Applications, Yasuhito Takahashi of Fujitsu described low cost plastic packaging for GHz devices, and focused on several varieties of built-up-multilayer (BUM) substrates to support flip chip packages with up to 3500 BGA connections, and ICs with 165 µm bump pitch.
Kazuhiko Iijima, also from Fujitsu, described the MV (multivia) technology for Wireless Applications. This family of substrates is an all build up technology with embedded passive components. The substrates use copper clad films, laser drilling, and selective plating to create plane pairs. Some varieties laminate completed films with adhesive layers containing conductor-filled laser drilled vias. Other substrates continue building up sequentially from the first layer of film. Thin passive components were selectively embedded in the adhesive-based technology.
Following a full day of technical presentations, the evening banquet featured toasts and speeches, much beer and sake, and splendid food, including enough sushi to feed an army.
Tuesday began with the session on Packaging Technology for Optical Communications Systems. Hideyuki Takahara described NTT's method of optical interconnection for flip chip ICs using an optoelectronic chip on flex with a 3-layer flex film with embedded optical waveguide The emphasis was on low thermal expansion material to allow precise alignment for a linear array. Very low loss was achieved with +/- 1 µm alignment accuracy.
A session on MEMS technology included an interesting look at the technology espoused by Ball Semiconductor, presented by Masataka Yoshida. As the company name implies, these folks are able to make ICs on the surface of 1 mm balls of silicon. They connect from one ball to another, and to the outside world, with rings of solder bumps. This radical technology eliminates the need for a cleanroom, as all processing is done within tubes.
The highlight of the afternoon was the opportunity to tour the NTT Telecommunication History Museum in Musashino. Starting with meticulously copied Western Electric electromechanical switching systems from the post-WW II era, NTT has evolved its own distinct, world class, leading edge technology. The museum is first rate, and well worth a visit.
Wednesday's first session was on future packaging technology. Len Schaper, of the University of Arkansas, compared several 3-D packaging technologies, and concluded that through-silicon vias in stacked thin ICs are a potential breakthrough technology that will enable new architectural possibilities because of the density of Z-axis interconnects.
Walter De Raedt, of IMEC, examined the potential for multilayer thin film substrates incorporating integrated passives to allow microwave system in package applications. He presented several examples of combiners, filters, power dividers, etc., implemented in the advanced substrate technology.
Tomonori Fujii, from ASET, discussed the chip joining and inspection technologies used to form 3-D silicon stacks. Gold/gold thermocompression bonding is effective even with 18 µm square gold bumps. The resulting 3 µm gap was underfilled with a composite material using .3 µm filler particles. ACF material was also used to connect the stack; 1 µm particles resulted in 20 - 30 particles per bump being trapped. SAM was used to detect voids in connection and underfill.
Toshiro Hiraoka of Toshiba presented perhaps the most novel talk of the workshop, in describing a method for creating wiring layers using photo-induced selective plating to make both wires and vias in a microporous sheet of polymer material. The 20 - 80 µm thick material is coated with a sensitizer, and then exposed. Where a via is desired, the exposure intensity is increased. Low intensity only affects the surface and allows a wire to be plated in the subsequent electroless plating step. The process can be double sided to create a flex-like structure. The material is impregnated with resin after the copper is plated. Though this development is at its early stages, the potential is most exciting.
Following another splendid bento box lunch, the workshop concluded with a session on Electronic System Integration for System Packaging. Two talks from the ASET laboratory were excellent. Osamu Ibaragi described the Optoelectronic Hybrid Integration Technology work. He showed an optoelectronic MCM (OE-MCM) using a waveguide film laminated to a circuit board, and providing .3 - .5 dB/cm loss for 100 Gb signals. He also described an optical fiber board in which a UV curable resin was cured by illumination from the optical fibers to be connected; the resulting cured resin formed the waveguide core. These cores were "clad" by applying a layer of a different resin.
Kenji Takahashi updated the ASET work on 3-D chip stacking with through-silicon vias on 20 µm pitch. They have done a great deal since their ECTC papers last year to reduce the voids in copper vias by plating improvements, both in current control and in chemistry. They still have problems in the handling of 50 µm thick wafers. They are examining ultrasonic gold-gold flip chip attach for chip stacking. An ASET goal for 2002 is to build an OE-MCM incorporating 3-D chip stacks.
Overall, this was an excellent workshop with truly leading-edge talks, at a splendid facility. Progress in packaging technology at the system level continues to deliver great strides in system performance.
- - - - - - Report submitted by Dr. Len Schaper, Director, High Density Electronics Center, University of Arkansas.
Photo captions:
Participants ready to enjoy their bento box lunch.
Listening to a speech before the banquet.
The assembled group in the auditorium.
The auditorium at NTT's excellent conference facility.