Advance Program
THE SIXTH
VLSI PACKAGING
WORKSHOP
OF JAPAN
Table-Top Exhibition will also be held.
Sponsored by
The IEEE Components, Packaging,
and Manufacturing Technology Society and
The National Institute for Standards and Technology
================================================
November 12 - 14, 2002
Kyoto Research Park
Kyoto, Japan
The VLSI Packaging Workshop of Japan held every second year
since 1992 in the ancient capital of Kyoto has become a well-known
international workshop of advanced packaging technologies. To
monitor the latest trend and focus on the future target, the committee
strongly urges you to attend this workshop and participate in
the discussion. Bring your latest research results and exchange
your opinion with internationally acclaimed experts from industry
and academia. Beside engineers involved with packaging, wafer
processing experts and circuit designers are cordially invited
to bring their breakthrough ideas to solve the current problems
of SiP and SoC.
The workshop will be held in English and each oral presentation
will be allowed 30 minutes including 10-minute discussion. Simultaneously,
Table-Top Exhibition will be held adjacent to the workshop hall.
General Chair: Atsushi Nakamura, Hitachi, Ltd.
Phone: +81-42-320-7324, Fax: +81-42-327-8631
E-mail: nakamura-atsushi4@sic.hitachi.co.jp
Vice Chair: Masahiko Kohno, Dow Chemical Japan
George Harman, NIST
Program Chair: Tomoshi Ohde, Sony Semicon. Kyushu Corp.
Exhibition Chair: Yasufumi Uchida, Oki Electric Industry
Nov. 12th (Tuesday)
9:00- Registration
9:50-10:30 Welcome & Invited talks
10:30-12:00 Session 1Printed Circuit Board
12:00-13:00 Lunch
13:00-15:30 Session 2 Interconnects & New Packages
15:30-16:00 Coffee Break
16:00-18:00 Session 3 Process
18:30- Welcome Party
Nov. 13th (Wednesday)
9:00-10:30 Session 4 Solder Joint
10:30-10:45 Short Break
10:45-12:45 Session 5 RF & Optoelectronics
12:45-13:45 Lunch
13:45-15:45 Session 6 Electrical Design (1)
15:45-16:15 Coffee Break
16:15-17:45 Session 7 Material
17:45-18:15 Snack & Beer
18:15-19:45 Session 8 Trends
Nov. 14th (Thursday)
9:00-10:30 Session 9 Electrical Design (2)
10:30-10:45 Short Break
10:45-12:45 Session 10 3D/Wafer-level Packaging
12:45-13:45 Lunch
13:45-15:45 Session 11 Topics
15:45 Closing Remarks
Please visit the website of the VLSI Packaging Workshop of
Japan for more information.
https://homepage1.nifty.com/ieeetokyo/chapter/cpmt/vlsip.html
Tuesday November 12
9:50-10:30 Welcome & Invited Talks
Chair: Kanji Otsuka, Meisei Univ.
0.1. Opening Remarks, Atsushi Nakamura, Hitachi, Ltd.
0.2. Microprocessor Packaging Challenges in Power Management,
Raj Nair, Intel Corp., USA
10:30-12:00 Session 1: Printed Circuit Board
Chair: Kimihiro Yamanaka
1.1. Development of the Novel Interconnection Technology for Multilayer
Substrate, Ryoichi Okada, Sumitomo Bakelite Co., Ltd.
1.2. Novel Laser Micro-Via Organic Substrate Technology for Semiconductor
Package, Hiroyuki Mori, Kaoru Kobayashi, Kimihiro Yamanaka, and
Yutaka Tsukada, IBM Japan
1.3. Development of Industrial Scale Manufacturing Line for Integrated
Module Board Technology, Risto Tuominen and Petteri Palm, N.N.,
Imbera Electronics Oy, Finland
12:00-13:00 Lunch
13:00-15:30 Session 2: Interconnects and New Packages
Co-Chairs: Yasufumi Uchida and Tadaaki Mimura
2.1. Development of Adhesive Enabling Replacement of Bare Chips
on PWB, Hideshi Tokuhira, Tomohisa Yagi, Hiroaki Date, and Eiji
Horikoshi, Fujitsu Laboratories Ltd.
2.2. Wire Bonding Analysis and Yield Improvements for Cu Low-K
IMD Chip Packaging, Tai-Chun Huang, Ming-Shouh Liang, Tze-Liang
Lee, Shin-Chang. Chen, Douglas C.H. Yu, and Mong-Song Liang, Taiwan
Semiconductor Manufacturing Company, Taiwan
2.3. Development of System-in-a-Package Utilizing Ultrasonic Flip-Chip
Bonding Technologies, Toshihiro Iwasaki, Keiichiro Wakamiya, Tatsuo
Nishihara, Yoshihiro Tomita, Yasumichi Hatanaka, and Michitaka
Kimura, Mitsubishi Electric Corp.
2.4. Development of MCP Incorporating a Highly Reliable Wafer-Level
Chip Size Package, Yoshimi Egawa, Oki Electric Industry Co., Ltd.
2.5. High-Density, Fine-Pitch CSP Based on Multi-Layer Thin Substrate
Technology, Katsumi Kikuchi, Tadanori Shimoto, Wataru Urano, Hironori
Ohta, Keiichiro Kata, and Kazuhiro Baba, NEC Corp.
15:30-16:00 Coffee break
16:00-18:00 Session 3: Process
Co-Chairs: Michitaka Kimura & George Harman
3.1. Process Control of the Reflow of AuSn Bumps, M. Hutter, H.
Oppermann, G. Engelmann, J. Wolf, O. Ehrmann, R. Aschenbrenner,
and H. Reichl, Fraunhofer IZM-Berlin, Germany
3.2. Development of the High Density Multiple Layers Wiring Package
Using a Photosensitive Polyimide, Katsuya Kikuchi, Shigemasa Segawa,
Eun-Sil Jung, Hiroshi Nakagawa, Kazuhiko Tokoro, Hiroshi Itatani,
and Masahiro Aoyagi, National Institute of Advanced Industrial
Science and Technology (AIST)
3.3. Innovative Material Deposition Technologies Using New Machine
Concepts Wafer Bumping, J. Kloeser, O. Dinse, J. Schmdt, R. Heynen,
and B. Lemmermeyer*, EKRA Eduard Kraft GmbH Maschinenfabrik, *Fachhochschule
Heilbronn, Germany
3.4. Probe Mark Effect on Fine Pitch Wirebonding, Hiromitsu Miyai,
IBM Japan
Wednesday, Nov. 13th
9:00-10:30 Session 4: Solder Joint
Chair: Tomoshi Ohde
4.1. A Study in Flip-Chip UBM/Bump Reliability with Effects of
Sn-Pb Solder Composition, Jenq-Dah Wu, Advanced Semiconductor
Engineering, Inc., Taiwan
4.2. Evaluation Method of the Impact Shear Strength for the Solder
Bump Bonded Interface in Semiconductor Encapsulation, Toshiaki
Morita, Hitachi, Ltd.
4.3. Environmental Impacts of Electronic Packaging Materials,
Nobuo Kamehara, N. F. Cooray, Hiroaki Date, Masayuki Ochiai, and
Eiji Horikoshi, Fujitsu Laboratories Ltd.
10:30-10:45 Short Break
10:45-12:45 Session 5: RF & Optoelectronics
Co-Chairs: Noboru Iwasaki & Phillip Garrou
5.1. Characteristics GaAs HEMTs with Flip-Chip Interconnection
Structure Using Underfill Resin, Yuji Iseki and Naoko Ono, Toshiba
Corp.
5.2. Multi-chip BGA Package with the Connectors for 40Gb/s MUX/DMUX
Chipset, Hideko Ando, Hiroshi Kikuchi, Satoru Isomura, and Norio
Nakazato, Hitachi, Ltd.
5.3. Development of an Optical Active Connector for LAN, Nobuyuki
Tanaka, Yukio Komine, and Yoshimitsu Arai, NTT Microsystem Integration
Laboratories
5.4. Inter-Chip Optical Interconnection Using Optoelectronic Integration
and Diffractive Optics, Takeshi Takamori, Hironori Sasaki, and
Hiroshi Wada, Oki Electric Industry Co., Ltd.
12:45-13:45 Lunch
13:45-15:45 Session 6: Electrical Design (1)
Co-Chairs: Toshio Sudo & Len Schaper
6.1. Development of a Non-Contact Current Distribution Measurement
Technique for LSI Packaging on PCBs, Kouichi Uesaka, Kenichi Shinbo
and Takashi Suga, Hitachi, Ltd.
6.2. Improvement of the Transmission Characteristic by the Embedded
Transmission Line, Yasuhiko Odate, *Chihiro Ueda, **Eiji Tanabe,
*Kanji Otsuka, and Tadatomo Suga, Univ. of Tokyo, *Meisei Univ.,
**AET Japan Inc.
6.3. EMI Reducing Techniques for Low Voltage Differential Signaling
on a Flexible Printed Circuit Board, Ayako Takagi and Haruhiko
Okumura, Toshiba Corp.
6.4. 10GHz Electrical Characterization and Limit of Organic BGA
Packages With and Without Plating Stub, Chih-Pin Hung, Advanced
Semiconductor Engineering, Inc., Taiwan
15:45-16:15 Coffee Break
16:15-17:45 Session 7: Materials
Chair: Masahiko Kohno
7.1. Study of Integrated Passive Components, Masahiko Ogino, Hitachi,
Ltd.
7.2. Polymer Integrated Circuits Based on Polyfluorene Derivatives,
Mitchell Dibbs and Phillip Garrou, Dow Chemical-Advanced Electronic
Materials, USA
7.3. Development of Assembly Technology for High Reliability Flip
Chip Package, Satoru Katsurayama and Hiroshi Watabe*, Sumitomo
Bakelite Co., Ltd., *Toshiba Corp.
17:45-18:15 Snack & Beer
18:15-19:45 Session 8: Trends
Chair: Fuminori Ishitsuka
8.1. Optoelectronic Manufacturing Trends in China, E. Jan Vardaman
and Timothy J. Urekew, TechSearch International, Inc., USA
8.2. Advances in 3D Packaging - Trends and Technologies for Multi-chip
Die and Stacking, Lee Smith, Y.W. Heo and Akito Yoshida, Amkor
Technology, Inc., USA
8.3. Advanced Semiconductor Packaging Solutions: CSP to SiP, Ann
Marie Pate, Tessera Technologies, USA
Thursday, Nov. 14th
9:00-10:30 Session 9: Electrical Design (2)
Chair: Kunihiko Nishi
9.1. Replacement of Bypass Capacitor to Transmission Line for
High Frequency Power Supply System, Keisuke Saito, Yutaka Akiyama*,
Tamotsu Usami, Kanji Otsuka*, and Tadatomo Suga, University of
Tokyo, *Meisei University
9.2. Simultaneous, Switching Noise of Wafer Level Packaging -
BGA for SRAM, Yutaka Uematsu, Hideki Osaka, Naoto Taoka, and Motoo
Suwa, Hitachi, Ltd.
9.3. Usefully Smart Power Supply Circuit, Chihiro Ueda, Yutaka
Akiyama*, Kanji Otsuka*, Tamotsu Usami**, Yasuhiko Odate**, and
Keisuke Saito**, AET Japan Inc., *Meisei University, **University
of Tokyo
10:30-10:45 Short Break
10:45-12:45 Session 10: 3D Packaging & Wafer level CSPs
Co-Chairs: Nobuo Kamehara & Jan Vardaman
10.1. Enabling Advanced VLSI Architectures Using Through -Silicon
Via 3D Layer Stack Technology, Leonard W. Schaper and Silke A.
Spiesshoefer, University of Arkansas/HiDEC, USA
10.2. 3D-Integration of Integrated Circuits by Interchip Vias
(ICV) and Cu/Sn Solid Liquid Interdiffusion (SOLID), P. Ramm*,
A. Kiumpp, and R. Wieland, Fraunhofer Institute IZM, Germany
10.3. Chip Size Module: Ultra High Integrated Device Module in
Wafer Level Packaging, Masamitsu Ikumo, Yoshitaka Abe, Osamu Igawa,
Tetsuya Fujisawa, Hirohisa Matsuki, and Mitsutaka Sato, Fujitsu
Ltd.
10.4. Superfine Flip-Chip Bonding Technologies for 3D Stacked
System-in-a-Package Utilizing Tin-Capped Cu Bumps in 20?m-pitch,
Masamoto Tago, Yoshihiro Tomita, Yoshihiko Nemoto, Kazumasa Tanida,
Mitsuo Umemoto, and Kenji Takahashi, Association of Super-Advanced
Electronics Technologies (ASET)
12:45-13:45 Lunch
13:45-15:45 Session 11: Topics
Co-Chairs: Atsushi Nakamura & Hirofumi Nakajima
11.1. Impacts of the Assembly Process to the Cu/LK IMD Chip Integrity,
Ming-Shuoh Liang, Taiwan Semiconductor Manufacturing Company,
Taiwan
11.2. Integrated CCD Micro-Camera System Module for Visual Inspection
Realized by High-Density 3D Microsystem-in-Package Technology,
Hiroshi Yamada, Takashi Togasaki, Atsushi Sadamoto, and Hajime
Sudo, Toshiba Corp.
11.3. A Full-Wave Simulator for the Design of Next-Generation
High Performance Systems, Steven L. Dvorak and John L. Prince,
University of Arizona, USA
11.4. Conceptual Simulator for Thermal Design of High Density
Electronics System, Y. Iwata, S. Yamamoto, S. Hayashi, and K.
Fujimoto, Osaka University
15:45 Closing Remarks
Access to Kyoto
The access to Kyoto is 75 minutes by express railway "Haruka"
from Kansai Int'l Airport. Another access from JR Tokyo station
is about 2 hours and half trip by using JR Tokaido Shinkansen
Line. Add one hour from Narita Int'l Airport to JR Tokyo station.
Venue
The workshop will be held at the Kyoto Research Park (East Building
#1, 4F Science Hall) located in the west area in Kyoto. Access
to the Kyoto Research Park is as follows.
- 10 minutes by taxi from JR Kyoto station
- 5-minute walk from Tanba-guchi station of JR San-in Line
- Buses are also available from JR Kyoto station
Address: 17, Chudoji, Minami-machi, Shimogyo-ku,
Kyoto 600-8813, Japan
Phone: +81-75-315-8665, Fax: +81-75-322-5348
URL: https://www.krp.co.jp/HP98Ehtml/
Accommodation
You can find a hotel list in the workshop website. Kyoto Royal
Hotel is a liaison hotel with the workshop. Room reservations
should be made directly to the hotel by using a reservation sheet
for the workshop. The room rate is as follows.
- Single room for single use: \12,000/ night
- Twin room for single use: \15,000/ night
- Twin room for twin use: \21,500/night
Address: Sanjo-agaru, Kawara-machi, Nakagyo-ku,
Kyoto 604-8005, Japan
Phone: +81-75-223-1234, Fax: +81-75-223-1702
URL: https://www.kyoto-royal.co.jp/indexe.html
Access to Kyoto Royal Hotel is 15 minutes by taxi from JR Kyoto
station, or 1-minute walk from Kyoto Shiyakusho-mae station of
Subway Tozai-Line. Courtesy buses between KRP and Kyoto Royal
Hotel are available only for those who stay Kyoto Royal Hotel
during the workshop. Timetable will be delivered at your check-in
the hotel. Kyoto is the best season to visit and see the autumn
foliage in November. Every hotel will be busy by many visitors.
Earlier reservation is strongly recommended.
Registration Fee
Before Oct. 18, 2002 (received date basis)
- IEEE members, speakers or session chairs \ 50,000.-
- Non-members \ 55,000.-
After Oct.19, 2002
- IEEE members, speakers or session chairs \ 55,000.-
- Non-members \ 60,000.-
The fee covers refreshment breaks, three luncheons, evening party
at first night, snack and beer at second night and a copy of the
Extended Abstract. It does not include hotel accommodation and
transportation from/to the Kyoto Research Park.
Payment
Payment of the Workshop fees should be made in Japanese Yen for
the total amount due in one of the following methods:
1. by Credit Card:
Either VISA or MasterCard is acceptable. Make sure the expiration
date of your card and fill in the attached Registration Form with
your authorized signature. Please print your name, card number,
and expiration date clearly in the form.
2. by Bank to Bank Transfer:
Make remittance to the following account without any charge for
the receiver. Remittance information to identify the sender is
required.
- Account Name: VLSI PACKAGING WORKSHOP
- Account Number: 0532625
- Bank Name: Katano branch (#579), Tokyo-Mitsubishi Bank (Tel:
+81-72-893-1213)
3. by Cash on site: (Not applicable for Advance Registration
rate)
Only effective for attendee who can use neither method #1 nor
#2. Please send the registration form by FAX in advance.
Confirmation for receiving your registration will be sent by
E-mail. Receipt will be provided at the Workshop Registration
Desk in the Kyoto Research Park.
Advance Registration Form
--The Sixth VLSI Packaging Workshop of Japan --
[Print clearly. Make enlarged copy of this form when using FAX.]
Dr./Mr./Ms. (first) (middle) (last)
Name: ___________________ ______ ____________________
Affiliation: ______________________________________________
Department: _____________________________________________
Address (office): _________________________________________
City: _____________________State: _______________________
Zip: _____________________Country:_______________________
Phone:(+_______) ________________________________________
Fax: (+_______) ________________________________________
E-mail:________________@________________________________
[E-mail address should be required! We will send the receipt confirmation
by e-mail.]
# Choose one if you are an IEEE member, speaker, or chair.
[ ] IEEE Member (No. ), [ ] Speaker, [ ] Chair
Total amount of payment: \ , 000-
# Choose one from the following payment methods.
1. [ ] I prefer to pay the total amount by Credit Card.
[ ] Visa, [ ] MasterCard, Other Credit cards not accepted.
Card Number: ______-______-______-______, Exp. Date: ___/___
Authorized Signature: ____________________,Date: ___________
2. [ ] I sent the total amount by Bank to Bank Transfer.
Account Name: VLSI PACKAGING WORKSHOP
Account Number: 0532625
Bank Name: Katano branch (#579), Tokyo-Mitsubishi Bank
Remittance date: _________________________________
Bank Name: _________________________________
3. [ ] I want to pay by Cash on site.
Please send this form to the following address by mail or FAX.
Mr. Tadaaki Mimura
Packaging Technology Develop. Group, Production Eng. Center
Semiconductor Company, Matsushita Electric Industrial Co., Ltd.
1, Kotari-Yaki-machi, Nagaokakyo-shi, Kyoto 617-8520, JAPAN
Phone: +81-75-956-9551, Fax: +81-75-953-7514
E-mail: mimura@sel.mec.mei.co.jp