The STS: IEMT is an international forum on electronic components and systems manufacturing technology. It is the second largest IEEE/CPMT packaging conference in the United States, and offers a unique venue for engineers and scientists to present and publish their original work. The conference features technical papers on research, development and applications of manufacturing technology for electronic components, assemblies and systems that has been selected by a committee of experts.

STS: IEMT Keynote Speaker: Joseph Adam
Wednesday July 16, 2003
9:00 AM - 9:45 AM

Joseph Adam
Vice President Technology Integration, Skyworks Inc. & Co-Chair, ITRS Packaging Technical Working Group
2003 ITRS Packaging Roadmap Overview

The talk will focus on the changing trends of package I/O counts, cost, frequency limits, power, and pitches both off-chip and off-package. The major technology challenges facing the industry in packaging substrates, design tools, new materials requirements, packaging of low K/Cu semiconductors, high frequency design will be described. Six emerging technology segments will be reviewed and the impact of these new segments on the industry will be discussed. These include System In Package, materials, embedded passives, substrates, optoelectronics packaging, and MEMS packaging. The impact that reduced packaging R& D spending and a sustained weak economy will have on the industry will be outlined.

STS: IEMT Session 201: Advanced Processing Technology
Wednesday July 16, 2003
10:00 AM - 12:30 PM

Session Chairs: Frank Juskey, AIT, Inc. & Dr. Belgacem Haba, Tessera

The key to cost reduction in IC packaging is the implementation of state of the art materials and processes to lower manufacturing costs. This session will offer a diverse selection of papers dealing with laser singulation of packages, new flux and under fill application techniques for flip chip processing, advanced methods of locating packages relative to saw streets, and in situ monitoring for improved processing yields.

Laser Singulation / Dicing of Chip Scale and Silicon Wafer Scale Packages, Todd Lizotte, NanoVia, LP

Unique Fiducial Designs for CSP Singulation Process, Prakorn Vijchulata, AMD (Thailand) Ltd.

Precision Flux Deposition Techniques for Semiconductor Applications, Stuart Erickson, Ultrasonic Systems, Inc.

An Innovative Underfill Process for High-Speed SMT CSP BGA Flip Chip Assembly, James Jian Zhang, Georgia Tech

An Acoustic Sensor for Monitoring Microelectronics Packaging Manufacturing Processes, Frances Williams, Georgia Institute of Technology

Study of Non-Solder, Low Cost and High Performance Flip Chip QFN Package Using Ultra Thin Pd PPF, Se Chuel Park, Samsung Techwin Ltd.

STS: IEMT Session 202: Novel Wire Bonding Techniques
Wednesday July 16, 2003
10:00 AM - 12:30 PM

Chairs: Paul Lin, & Peter Harper, Motorola Semiconductor Products Sector

In order to implement Fine Pitch Wire Bonding (50 um pitch or less), many technical issues have to be resolved. Some are directly related to FPWB itself such as FPWB transducer, FP wire diameter and FP capillary. Others are indirect issues such as FPWB yield and its long term reliability, FP wire pull characterization even using in-situ ball shear monitoring. In this session, authors from IDM, end user, equipment & material suppliers and assembly contractor will jointly discuss practical solutions to these issues.

Reliability Ground Rules Change at <50 mm Pitch, Inderjit Singh, NVIDIA Corp.

The Challenge of Testing Ultra Fine Pitch Wire Bonds, Robert John Sykes, Dage Precision Industries Ltd.

Novel Ultrasonic Transducer Design for Fine-Pitch Wire-Bonding, Martin von Arx, ESEC SA

NoSWEEP Technology for Wire Bonding PBGA Applications, Andrew Hmiel, Kulicke & Soffa Industries

In Situ Ball Bond Shear Measurement Using Wire Bonder Bondhead, Jonathan Medding, ESEC SA

Effect on Leadframe Design on Aluminum Wire Bonding, Tan Joo Hong, Infineon Technologies Asia Pacific Pte Ltd.

STS: IEMT Poster Session
Wednesday July 16, 2003
12:30 PM - 2:00 PM

Chair: Leo Higgins, ASAT Inc.

Poster Sessions have been proven to be a successful means of promoting both research activities as well as currently available technologies. Posters allow a broad viewing audience to access the various informational content topics based upon an individuals interest level and time availability. Session attendees can spend as much or as little time as they like at each of the Posters, as the session timing is non-structured by design to promote open communication. This is an excellent opportunity for the one-on-one discussions between attendees and authors or technical representatives in addressing questions or comments on technologies presented. Please take this opportunity to attend and enjoy the Poster Session, as it is another networking venue format, keeping in mind that your feedback on the Poster Session is also appreciated.

Epoxy Flux --An Answer For Reliable No-Clean Flip Chip Assembly, Ning-Cheng Lee, Indium Corporation of America

Considerations for Minimizing Radiation Doses to Components during X-ray Inspection, Richard C. Blish, II, AMD, Inc.

Extreme High Speed Microvia Drilling Of Chip And Wafer Scale Packaging Products, Todd Lizotte, NanoVia, LP

Control of Solutions for Electrodeposition of Bumps, Peter Bratin, ECI Technology

X-Ray Inspection, Udo Frank, Ph.D., feinfocus Rontgen-Systeme GmbH

Encapsulation of Sensorchips with Advanced Transfer Molding, Anton van Weelden, Boschman Technologies

STS: IEMT Session 203: "Green" Manufacturing of Electronics
Wednesday July 16, 2003
2:00 PM - 5:30 PM

Chairs: Luu Nguyen, National Semiconductor & Brian Toleno, Loctite

"Green" manufacturing has gained interest in the last few years as the industry moves to eliminate lead and halogen compounds from packages and assembly processes. Much of the earlier interest came from consumer electronics demands in Asia. However, with the recently published WEEE Directive, green products are now mandated in Europe beyond July 2006. This timely session covers issues on halogen-free packaging, and lead-free processes related to flip chip and CSP assembly, soldering, and board level reliability.

Qualification & Optimization of Sn Based Soft Solders: A Refinement for Bi Based Leadfree Soft Solders for EFM Volume Production, Bryan Y. Y. Ong, ChipPAC, Malaysia Sdn Bhd

Epoxy Flux For Lead-Free Soldering, Ning-Cheng Lee, Indium Corporation of America

Implementation of Pb-Free Bump Interconnect in Power Packaging, Rajeev Joshi, Fairchild Semiconductor Corporation

Lead Free Package Interconnections for Ceramic Grid Arrays, Mario Interrante, IBM Microelectronics Division, Interconnect Products

Investigation on a Lead-Free Flip Chip Assembly Process, Gerard Kums, Philips Centre for Industrial Technology

Inter-Dependence of Processing and Alloy Composition on the Reliability of Sn-Based Lead- Free Solders in Fine Pitch FCOB Interconnection, Dr. Changqing Liu, Wolfson School of Mechanical and Manufacturing Engineering

Towards a Halogen-Free Package - GREEN Molding Compound, Joanne Kee, Infineon Technologies Asia Pacific Pte Ltd.

STS: IEMT Session 204: Package Design & Characterization
Wednesday July 16, 2003
2:00 PM - 5:30 PM

Chairs: Atila Mertol, LSI Logic & Nirmal Jain, Rambus

Package design, mechanical, thermal and electrical modeling and manufacturability of electronic packages become an integral part of the design process for robust package design and cost reduction. This session includes papers that describe methodology to generate compact models of packages and heat sinks from modeling, measurements, electrical performance comparison of wire bonded and flip chip packages, signal integrity analysis and advanced substrates for high speed and high performance packages, design of manufacturability and cost reduction.

A Methodology for the Generation of Dynamic Compact Models of Packages and Heat Sinks from Thermal Transient Measurements, Marta Rencz, Budapest University of Technology and Economics Department of Electron Devices

A Comparison of Electrical Performance between a Wire Bonded and a Flip Chip CSP Package, Rahul Kapoor, United Test and Assembly Center Ltd.

An Approach to Reduce Build Up Layers for Flip Chip - Ball Grid Array (FC-BGA) Substrates, Toshihiko Nishio, IBM Microelectronics Division

An Advanced Packaging Solution for OC-768, 40Gb/s Utilizing IBM Standard Alumina MLC Technology, Warren D. Dyckman, IBM Microelectronics Division, Interconnect Products

Modeling and Simulation of 12.5 Gb/s on a HyperBGA Package, Steven G. Rosser, Endicott Interconnect Technology, Inc.

A Design And Performance Study of 3D Packaging for High Performance Memory Applications, Ilyas Mohammed, Tessera Technologies, Inc.

STS: IEMT Session 205: Wafer Level Packaging
Thursday July 17, 2003
9:00 AM - 12:15 PM

Chairs: Jan Vardaman, TechSearch International & Erik Jung, FhG-IZM

Packaging at the wafer level is gaining momentum, especially for low I/O count applications. This session focuses on developments in wafer level packaging (WLP). Presentations provide prospective from WLP users in terms of package needs and requirements. New data from suppliers, including package construction, materials, reliability, and manufacturing issues will be presented. Highlighted are the issues with back-end assembly for wafer level packages.

A New Wafer Level Package Having Solder Bumps On Polymer Structure, Scott Barrett, Kulicke & Soffa Flip Chip Division

New Advancements in Photoimageable Dielectric Resins for Wafer Level CSP Applications, Christopher Esposito, Shipley Far East Ltd.

Time Dependant Materials Issues in the Electromigration of Solder Bumps, Glenn Rinne, Unitive Inc.

Wafer Level Packaging-Reliable Solutions for Evolving Market Requirements, Scott Barrett, Kulicke & Soffa Flip Chip Division

WLCSP Back-End Considerations, Ted Tessier, ST Assembly Test Services Inc.

Backend Processing for Wafer Level Chip Scale Packaging, John Hunt, ASE (US) Inc.

A Memory Suppliers Outlook on Die Products, Dan Skinner, Micron Technologies

STS: IEMT Session 206: Manufacturing Test
Thursday July 17, 2003
9:00 AM - 12:15 PM

Chairs: Omy Ronquillo, NP Test & Allan Calamoneri, Test Spectrum

The increasing portion of IC packaging and test cost remains a major concern to the IC manufacturing management. Significant advances in the semiconductor manufacturing technologies and IC design continue. This enables exciting developments of new applications and product functions leaving enough challenges to the testing world.

Overcoming Test Challenges Presented by Embedded Flash Memory, Thomas M. Trexler and Jim Agin, Credence Systems Corporation

Reduce Your Cycle Time By Utilizing Automation for Wafer Test Data Collection, Navin Tandon, Texas Instruments

Current Challenges in Transistor Level Design Verification and its Application in Flip Chip Packaged Devices, Itzik Goldberger, Optonics, Inc., A Credence Company

Open Architecture Test System: The New Frontier, Sergio Perez, Advantest America, Inc.

Technical and Economic Requirements of Integrated SOC Testing, Don Blair, Agilent Technologies

Validating and Characterizing High-Speed Datacom Devices, Tom Napier, NPTest

Reducing the Cost of Package Test, Saeed R. Shakeri, Advanced Interconnect Technologies, Inc.

STS: IEMT Poster Session
Thursday July 17, 2003
12:15 PM - 2:00 PM

Chair: Leo Higgins, ASAT Inc.

Poster Sessions have been proven to be a successful means of promoting both research activities as well as currently available technologies. Posters allow a broad viewing audience to access the various informational content topics based upon an individuals interest level and time availability. Session attendees can spend as much or as little time as they like at each of the Posters, as the session timing is non-structured by design to promote open communication. This is an excellent opportunity for the one-on-one discussions between attendees and authors or technical representatives in addressing questions or comments on technologies presented. Please take this opportunity to attend and enjoy the Poster Session, as it is another networking venue format, keeping in mind that your feedback on the Poster Session is also appreciated.

Increased Levels of Integration Drive the Need for New Test Approaches in Wireless Designs, John Lukez, Credence Systems

Integrated Cellular Transceivers: Challenging Traditional Test Philosophies, Edwin Lowery, Agilent Technologies

Testing High-Speed Serial Interface Technology: Is Your Test Solution in Synch?, Steve Lomaro, NP Test

The Daily Living with "Monster" Probe Cards, Frank Pietzschmann, Infineon Technologies AG

Advanced Manufacturing Techniques for Flip Chip Devices, Gheorghe Pascariu, Newport Corporation

STS: IEMT Session 207: Advanced Packaging: Flip Chip, 3D, and SiP
Thursday July 17, 2003
2:00 PM - 5:30 PM

Chairs: Jeffrey Demmin, Tessera Technologies, Inc. & Vijaylaxmi Gumaste, National Semiconductor

Many of the significant advances in the functionality and density of today's electronic products are the result of advanced packaging technology that continues to push the limits of the industry's capabilities. This session examines issues related to flip chip, advanced design, system-in-package approaches, and 3D technologies that are driving these advances. All of the papers are focused on high-volume manufacturing, so these are real technologies, not just investigations into the possibilities.

3D Stacked Packages With Bumpless Interconnect Technology, Charles W. C. Lin, Bridge Semiconductor Corporation

Flip Chip on Standard Lead Frame: Laminate Performance at a Lower Cost, Frank Juskey, Advanced Interconnect Technologies

Stacked Chip Scale Packages: Manufacturing Issues, Reliability Results, and Cost Analysis, Jeffrey C. Demmin, Tessera Technologies, Inc.

Improved Application Capabilities as a Result of Flip Chip PBGA Technology Development Advancements, Ron Malfatt, IBM

The Technology Benchmarking Study of System-in-a-Package (SiP), Edward Law, ST Assembly Test Services Inc.

WLAN LTC Modules; Advanced Design, Technologies and Manufacturing, Nicolas Gosselin and Stanley Wang, DT Microcircuits

Package Stacking in SMT for 3D PCB Assembly, Dongkai Shangguan, Ph.D., Flextronics

STS: IEMT Session 208: Reliability & Advanced Materials
Thursday July 17, 2003
2:00 PM - 5:30 PM

Chairs: Reza Ghaffarian, JPL & Harvey Miller, Infrafocus

Reliability and qualification tests are required to be performed when new materials and package techniques are developed. Advanced materials are developed to address un-met needs for better package electrical and thermal performance and reduced cost. They also must meet rigorous tests and reliability qualification for replacement. The papers in this session address not only materials and process; they also provide second level reliability and qualification to meet product implementation. Some of the issues discussed include: use of corner staking to improve reliability of CSP without underfill, reliability characterization for an RF module, process and material characterization and improvement to control thin laminate warpage and via integrity, and flip-chip format trade-offs.

X-BMI Resins as Low-Stress Alternatives to Epoxies for Semiconductor Package Assembly, Chris Perabo, Henkel Loctite Electronics

The Impact of Moisture in Mold Compound Preforms on the Warpage of PBGA Packages, Leon Lin Tingyu, Motorola Innovation Centre

High Reliability BGA Package Improvements on Module Total Cost of Ownership, Kim Blackwell, Endicott Interconnect Technologies Inc.

Manufacturing Issues for 3D Integrated Active Crcuits into Organic Laminate Substrates, Erik Jung, Fraunhofer IZM

Characterization of In-Process Substrate Warpage of Underfilled Flip Chip Assembly, James Jian Zhang, Georgia Tech

Processing and Reliability of Corner Bonded CSPs, Brian J. Toleno, Loctite Electronics

Board Level Reliability Evaluation of RF PA Module Vias, Robert Darveaux, Amkor Technology, Inc.

STS: IEMT Session 209: Wafer Bumping Technologies
Friday July 18, 2003
9:00 AM - 12:00 PM

Chairs: Bill Chen, ASE & Annette Teng Chueng, Ph.D., Corwil Technology

Wafer Bumping is a critical to IC assembly in flip chip. This session will be devoted to the advances in wafer bumping process technology, including novel process for 300 mm wafers, etching of UBM films, improvements in printing, advances in metal deposition & reflow processes, and new applications.

Characterization and Use of Spray Acid Tools for Large Volume Selective Etching of UBM Films Used in Flip Chip Applications, Lakshmi N. Ramanathan, Motorola Inc.

Wafer Bumping Technology for LDI Application by Electroless Nickel Plating, Joong-Do Kim, Samsung Techwin Co., Ltd.

A Novel Gold Deposition Process for Wafer Applications, Eugene B. Douglass, Shipley

Advances in 300mm Wafer Level Packaging--New Concepts of Material Deposition Technologies, Thomas Oppert, EKRA Eduard Kraft GmbH

Bumping Wafers via Ultrasonically Enhanced Stencil Printing, Gerald Pham-Van-Diep, Cookson Electronics Equipment

The Benefits of a Flux-Free Atmosphere for Wafer Bump Reflow, Fred Dimock, BTU International

STS: IEMT Session 210: Factory Simulation, Automation and Integration
Friday July 18, 2003
9:00 AM - 12:00 PM

Chair: Mohammad Khan, AMD & Orion Starr, ChipPAC

Time to market is the key today in a tough business environment. To achieve profitability flawless execution is essential. Rapid availability of information has cut profitability windows even smaller. For flawless execution, planning and cost studies must be carried out in detail. Process and factory simulation tools are used by leading companies to explore all available options before committing resources. Today's competitive environment does not allow changes to be made to either the factory or the product without serious financial consequences.

This session will cover papers from around the world from authors from leading companies. You will learn how these companies used leading methodologies for rolling out new products.

Customer Driven Innovation Process, Robert Pennisi, Motorola Inc.

Universal Simulation Kit in Micro-Production, Ortun Wiechers, Fraunhofer IPA

Equipment Failure Definition: A Prerequisite for Reliability Test and Validation, Tom Umberg, Delta Design

Pre-Project Facility Layout Planning for Setting-Up Cost Effective Wafer Bumping Process, Wu Ming, ST Assembly Test Service Ltd.

System Availability and Operation Support Modeling, Alex Fashandi, Delta Design

Cycle Time and Variability Reduction in an Optical Assembly Process, Salil Pardhan, Sanmina-SCI Corp.

Towards Next-Generation Design-for-Manufacturability (DFM) Frameworks for Electronics Product Realization, Manas Bajaj, Georgia Tech

Registration:

For more information, and to register, visit: www.semi.org/semiconwest/stsiemt

Complete Package (SEMI/IEEE Members)
Event Code: P6
Pre-Registration by July 7: $350
After July 7 or Onsite: $450

Complete Package (Non-Members)
Event Code: P7
Pre-Registration by July 7: $400
After July 7 or Onsite: $500

Complete Package (Students)
Event Code: P13
Pre-Registration by July 7: $100
After July 7 or Onsite: $150

Complete Package (Speaker/Chair/Committee)
Event Code: P8
Pre-Registration by July 7: $200
After July 7 or Onsite: $300

Wednesday Only (All Attendees)
Event Code: P9
Pre-Registration by July 7: $300
After July 7 or Onsite: $400

Thursday Only (All Attendees)
Event Code: P10
Pre-Registration by July 7: $300
After July 7 or Onsite: $400

Friday Only (All Attendees)
Event Code: P11
Pre-Registration by July 7: $200
After July 7 or Onsite: $300

Registration includes STS:IEMT proceedings CD and coffee breaks.

STS: IEMT is co-produced by SEMI & IEEE's CPMT