Rajen Chanchani now Fellow of Institute

Rajen Chanchani has been elected as IEEE-Fellow for his contribution to the development of advanced packaging concepts including technologies for high density interconnects, chip-scale-packages, micro-system integration, multichip modules and substrates, and for outstanding contribution and leadership in serving IEEE-CPMT society.

Rajen has received his Ph.D. and M.S. in Material Science & Engineering from the University of Florida. Since 1990, Rajen is working at Sandia National Labs in Albuquerque, New Mexico. Prior to that, Rajen worked for 5 years at AT&T Bell Labs, which was then the parent company of Sandia National Labs.

Rajen is an elected member of of the Board of Governors, he has chaired CPMT Technical Committee on Materials & Processes and organized several IEEE-CPMT sponsored conferences. Rajen has developed and published in 1994 a pioneering wafer-level chip-scale-packaging concept, which has revolutionized IC packaging. Rajen has developed new concepts for packaging of advanced micro-system for use in National Security applications. This effort has led to several innovations including (i) integration of microfluidics with microelectronics and sensors, (ii) Tamper-resistant multichip modules, and (iii) Integrated Substrate Technology and System-on-chip. Rajen has published over 50 technical papers and has two patents.