Future Directions in IC and Package Design Workshop (FDIP'04)
Oct. 24, 2004 in Portland, OregonThe fourth FDIP workshop had record attendance of 80 participants on Sunday, Oct. 24, 2004, in Portland, OR. This matched the very well attended EPEP'04 conference that followed for the three days, on Oct. 25-27, namely 190. The very interesting sessions were chaired by Ravi Kaw from Agilent Technologies, Prof. Hartmut Grabinski from University of Hannover, and Zhaoqing Chen from IBM Corporation. All the presentations were given by experts in the field that were invited to the workshop. The topics that were covered fell in three categories, System Design Challenges, Modeling Challenges, and Simulation Challenges.
The first session was started by Shekhar Borkar from Intel Corporation. The title of the talk was Gigascale Integration - Design Challenges and Opportunities. Shekhar outlined all the challenges faced by future chip designers in order to achieve the 1 TIPS goal by 2010 while not exceeding the 100W power limit imposed by the package. Although 1 billion transistors will be available on one die, due to leakage and all the other tolerances, new means need to be devised to utilize all the integration improvements. Such approaches were suggested as low power designs, higher integration of slow devices, tri-gate devices with 10x lower leakage, high-K, metal gate, multiple supply rails, body bias control, sleep transistors, variation-tolerant circuits. Micro-architectural changes are envisioned such as multi-threading, multiple cores, deep pipelining, increased on-chip caches. Heterogeneous systems with optical and RF brought on the same die (SOC) or on the same carrier (SIP) with the CMOS processors. Processors could have the traditional functions that are augmented by many special purpose CPUs.
The second talk, entitled Emerging Trends in High-Speed Interconnects and Packaging Engineering, was given by Sergio Camerlo from Cisco Systems. Sergio addressed the issue of increased design cycles due to signal, power, and timing integrity issues. All aspects of the system design are becoming more complex and yet technological improvements, such as printed circuit material properties, are not keeping up with the higher integration capabilities. Future designs need multi-disciplinary efforts with a convergence of circuit theory, electromagnetics, mathematics, numerical simulation, thermo-mechanical optimization. Sergio saw the need for smart I/O buffers, self-timed and de-skewed circuits, self-diagnostic capability on chip since of-chip testing is no longer possible or adequate, use of communication techniques, statistical designs, chip-package co-design, SIP, MCP, 3D stacking, intelligent power management, on-die temperature sensors, development of new model libraries and CAD tools.
The third talk was presented by Martin Schmatz of IBM Corporation and was entitled Analog RFCMOS and Optical Design Techniques for 10+ Gbps Datacom. The main issue that Martin addressed was the fact that in spite of the extremely high integration level on-chip, the I/O technology for communication between chips is lagging behind. His view is that we need Tbyte/sec/inch rates for the 1 TIPS chips in 2010. In order to achieve this, novel technologies have to be developed such as I/O density being pushed to 2-mil pitch and high-speed, small I/O cells interfacing directly with the I/O connections. Such density would drive development of new SIP technologies. Board-level optical interconnects are expected to appear in commercial high-end systems toward the end of the decade through the use of multi-mode waveguides having 30-70 um pitch and wavelength of 850 nm and embedded microlenses to couple to electrical interconnects in the board. Such optical interconnects will need much simpler channel equalization circuits than electrical counterparts and thus higher data-rates.
The second half of the workshop addressed the future modeling and simulation tool development requirements. Power Distribution Status and Challenges was presented by Prof. Madhavan Swaminathan of Georgia Institute of Technology. Due to the need to reduce the power distribution effective impedance by a factor of 2x for every product generation, new design tools, new technologies, and new decoupling schemes are needed. Heterogeneous systems lead to a chip-package co-design, time and frequency-domain analysis interchange, new embedded decoupling materials such as BatiO3 in the printed circuit boards, and in laminate-based chip carriers, the use of FDTD, TMM, device macromodels to include non-linear simulation of interconnect and power distribution noise, novel EBG structures included in large boards to isolate RF and digital circuits.
Ching-Chao Huang from Optimal Corporation presented the talk entitled Signal Integrity Modeling and Simulation for IC/Package Co-Design. Ching-Chao echoed the message given by all the previous speakers for the need of chip-package co-design and he reviewed the available tools that can be used for modeling and simulation of such complex systems. DC power drops, electromigration, as well as simultaneous switching noise, power plane resonances, and isolation have to be modeled for the chips and the package structures together. Signal and power integrity have to be optimized concurrently and microwave and RF design techniques have to be adopted by the digital circuit designers. Full-chip and full-package CAD tools need to include full-wave effects and still deliver 24 hour turn-around analysis time for the many design iterations. Several tools available from Optimal Corporations were shown as examples.
The last session was shortened by the typhoon and earthquake that was taking place in Japan. Sani Nassif was unable to travel to the US and Jaijeet Roychowdhury from University of Minnesota had to deliver the Current and Future Direction in Simulation Development talk alone. His talk was extremely well received and generated very interesting discussions. Jaijeet indicated that simulator development is gaining again momentum and progress due to the increasing demands of high integration levels, speeds, and heterogeneous systems. These new demands can be addressed by using modular approaches to algorithmic development for ease of use, maintenance and interoperability. He traced the evolution of SPICE and gave examples of new simulators such as FREEDA and gEDA that offer open-source methodologies that he thought were critical for future progress.
The workshop was followed by a very interesting IEEE CPMT Society Technical Committee on Electrical Design, Modeling, and Simulation (TC-EDMS) meeting chaired by Prof. Madhavan Swaminathan from Georgia Institute of Technology. The meeting covered among other topics a discussion led by Ravi Kaw of Agilent Technologies on power-distribution modeling standardization and a discussion led by Prof. Paul Franzon of North Carolina State University on the development of new device macromodels to advance the current IBIS capabilities.Photos:
Ravi Kaw, Agilent Technologies
Harmut Grabinski, University of Hannover
Zhaoquing Chen, IBM Corporation
Shekhar Borkar, Intel Corporation
Martin Schmatz, IBM Corporation
Madhavan Swaminathan, Georgia Institute of Technology
Ching-Chao Huang, Optimal corporation
