N3D2  Tracking and Photon Counting Circuits

Wednesday, Nov. 4  16:30-18:10  San Diego

Session Chair:  Stefan Ritt, Paul Scherrer Institute, Switzerland; Yasuo Arai, KEK, Japan

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(16:30) N3D2-1, A 10 Bit Resolution Readout Channel with Dynamic Range Compression for X-Ray Imaging at FELs

D. Comotti1,2, M. Grassi1,2, L. Lodola1,2, P. Malcovati1,2, L. Ratti1,2, C. Vacchi1,2, L. Fabris1,3, M. Manghisoni1,3, V. Re1,3, G. Traversi1,3, G. Batignani4,5, S. Bettarini4,5, G. Casarosa4,5, F. Forti4,5, F. Morsani4,5, A. Paladino4,5, E. Paoloni4,5, G. Rizzo4,5, M. E. A. Benkechkache6,7, G.-F. Dalla Betta6,7, R. Mendicino6,7, L. Pancheri6,7, H. Xu6,7, G. Verzellesi8

1INFN, Sezione di Pavia, Pavia, Italy
2Dipartimento di Ingegneria Industriale e dell'Informazione, University of Pavia, Pavia, Italy
3Dipartimento di Ingegneria e Scienze Applicate, University of Bergamo, Bergamo, Italy
4Dipartimento di Fisica, University of Pisa, Pisa, Italy
5Sezione di Pisa, INFN, Pisa, Italy
6Dipartimento di Ingegneria Industrial, University of Trento, Trento, Italy
7TIFPA, Trento, Italy
8Dipartimento di Scienze e Metodi dell Ingegneria, University of Modena and Reggio Emilia, Reggio Emilia, Italy
This work is about the experimental characterization of the first prototype of a readout channel for silicon pixel detectors developed by the PixFEL collaboration in view of future X-ray Free Electron Laser applications. The circuit, fabricated in a 65 nm CMOS technology by TSMC, has been designed to deal with a maximum input signal of 10000 photons with energy from 1 keV to 10 keV, by exploiting a non-linear technique implemented at front-end level. Moreover, it has been envisioned for operations compliant with the demanding frame rates of FEL facilities, of the order of a few MHz. This paper presents results of measurements performed on the building blocks of the readout processor, along with a summary of the overall characteristics of the complete readout channel.

(16:50) N3D2-2, VERITAS 2: a Multi-Channel Readout ASIC for pnCCD and DEPFET Arrays, Optimized for the Wide Field Imager for Athena

M. Porro1, D. Bianchi1, G. De Vita1, S. Herrmann2, A. Wassatsch3, A. Baehr1, N. Konaraddi1, N. Meidinger1, S. Ott1, J. Treis3

1Max Planck Institut fuer Extraterrestrische Physik, Garching, Germany
2SLAC National Accelerator Laboratory, Menlo Park, USA
3Halbleiterlabor der Max-Planck-Gesellschaft, Munich, Germany
VERITAS 2 is a multi-channel readout ASIC both for pnCCDs and DEPFET arrays. The VERITAS 2 chips are also able to cope with a large variety of operating conditions that may require very different input dynamic ranges and noise thresholds. The DEPFET pixels can be read-out in source follower configuration, i.e., reading out the voltage step on their source nodes, or in common source configuration, i.e., acquiring the drain current of the devices. VERITAS 2 is the first ASIC able to readout the DEPFET sensors both in source follower mode and in current drain mode. The first prototype of the ASIC, VERITAS 2.0, is already available and has been experimentally characterized. The ASIC is realized in the AMS 0.35µm CMOS 3.3 V technology and is composed of 64 analog readout channels able to process in parallel the signals coming from 64 pnCCD anodes or 64 DEPFET outputs. The analog channels are based on a fully differential architecture. In the drain current readout mode, it should be possible to obtain a readout time per row of about 2-3 µs with an electronics noise =5 electrons r.m.s. This readout scheme option has been specifically introduced in order to make the ASIC compatible with the challenging requirements of the Wide Filed Imager of Athena which will be the next large class X-ray observatory of the European Space Agency. The ASIC is also suitable for the new Fast Solar Polarimeter under development by the Semiconductor Laboratory of the Max Planck Society in collaboration for the Max Planck Institute for Solar System Reasearch. The large variety of gain settings enables spectroscopic modes with excellent noise performance but also high dynamic range modes for imaging with excellent resolution. This makes the ASIC especially versatile for Photon Science with pnCCD and DEPFET matrices used as photon integrating detectors. In the presentation, the main stages of the circuit and the experimental results on the ASIC coupled with large sensor arrays will be discussed.

(17:10) N3D2-3, SFERA: a General Purpose Readout IC for X and Gamma-Ray Detectors.

F. Schembari1,2, R. Quaglia1,2, G. Bellotti1,2, C. E. Fiorini1,2

1Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy
2INFN, Sezione di Milano, Milan, Italy
This work presents SFERA, a multichannel low-noise readout ASIC designed for both X and ?-ray detectors for spectroscopy and imaging applications. The chip has been developed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of Silicon Drift Detectors (SDDs) and CUBE charge preamplifiers, although we think this ASIC may find a wider application also with other detector solutions. The use of SFERA can range from high-resolution and high-throughput X-ray spectroscopy to scintillator-based ?-ray detection, thanks also to its flexibility and full programmability. The chip is able to accommodate five different energy ranges, when used with SDDs and a 25 fF feedback capacitance CMOS preamplifier: 10, 16, 36 and 50 keV for X-ray photons and a maximum of 20000 e- in the case of scintillation light detection. Filters shaping-times are also programmable among 0.5, 1, 2, 3, 4 and 6 μs. The analog section of the IC comprises a bank of 16 readout channels made of 9th order semi-Gaussian shaping-amplifiers followed by peak detectors, while the digital section includes all the logic responsible for the peak detectors synchronization, pile-up rejection and for driving the multiplexer. Three different data multiplexing strategies are implemented: the so-called polling-X, in which the MUX cyclically samples 4, 8 or 16 channels at 10 MHz, the burst mode (or polling-γ) in the case of γ detection and finally the sparse readout, used for signals derandomization purposes in conjunction with a dedicated channel-address logic. A Successive-Approximation ADC has also been integrated to eventually digitize the multiplexed data stream out. SFERA is implemented in AMS 0.35 μm CMOS process and its area occupancy is 25 mm2. A description of inner blocks and of the different data multiplexing strategies is here presented together with spectroscopic measurements results using SDDs and CUBE preamplifiers.

(17:30) N3D2-4, MiniVIPIC: Pixel Readout Integrated Circuit with on-Chip Charge Cluster Reconstruction for X-Ray Photon Science

S. L. Holm1, G. W. Deptuch1, F. Fahim1, P. Grybos2, J. R. Hoff1, P. Kmon2, P. Maj2, D. P. Siddons3, R. Szczygiel2, M. Trimpl1

1EED-PPD, Fermi National Accelerator Laboratory, Batavia, IL, USA
2AGH-UST, Krakow, Poland
3Photon Sciences Directorate, Brookhaven National Laboratory, Upton, NY, USA
A prototype pixel readout integrated circuit, featuring reconstitution of full signals from shared charge collected by neighbouring pixels, has been designed in a 130 nm CMOS process for X-ray science applications. It utilizes the C8P1 algorithm to allocate the hit to a single pixel and also allows for simultaneous time of arrival measurement. It consists of two paths, the first path is created from faster continuous, analog summing of amplified charge shares through the fast trim able discriminator. The second path is triggered by the first path which allows parallel comparisons of amplitudes of slower pulses between neighbours to allocate the hit to a selected pixel. Both slow and fast pulses are formed in semi-Gaussian filters of different time properties. The chip contains an array of 32×32 pixels; each pixel is 100×100 um2. The prototype is a test platform for the algorithm before its final implementation in a three-dimensionally integrated circuit.

(17:50) N3D2-5, VIPIC: a Custom-Made Detector for X-Ray Speckle Measurements

D. P. Siddons1, A. K. Rumaiz1, G. Deptuch2, P. Maj3, A. N. Kuczewski1, G. Carini4, S. Narayanan5, E. Dufresbe5, T. Aziz1, A. Sandy5, R. Bradford5, A. Fluerasu1, M. Sutton6

1National Synchrotron Light Source II, Brookhaven national Laboratory, Upton, NY, USA
2Fermi National Accelerator Laboratory, Batavia, IL, USA
3AGH-UST, Krakow, Poland
4SLAC National Accelerator Laboratory, Menlo Park, CA, USA
5APS, Argonne National Laboratory, Argonne, IL, USA
6Physics Dept., McGill University, Montreal, Quebec, Canada
We have developed a new detector, designed from the ground up to facilitate X-ray Correlation Spectroscopy (XCS) experiments. The device uses state-of-the-art silicon technology [1] to allow continuous, zero dead-time measurements with microsecond resolution. The detector only delivers non-zero data, greatly reducing the communications overhead typical of conventional frame-oriented detectors such as CCDs. The paper will describe how this is achieved and show preliminary data taken at APS, which verifies its suitability for continuous measurements from microseconds to hours. We will also indicate our plans for future developments along these lines.