Recently, CMOS downsizing has been accelerated very aggressively, and even normal transistor operation of a 6 nm gate length p-channel MOSFET was reported last year. However, many serious problems are expected for implementing such small-geometry MOSFETs into large scale integrated circuits, and it is still questionable whether we can successfully introduce sub-10 nm CMOS LSIs into the market or not. In this presentation, CMOS downsizing toward sub-10 nm is discussed, considering the expected problems for the integration.

Hiroshi Iwai received the B.E. and Ph.D. degrees in electrical engineering from the University of Tokyo, Japan in 1972 and 1992, respectively. Dr. Iwai is a professor of the Dept. of Advanced Applied Electronics, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology, Nagatsuta, Yokohama, Japan. He is also a professor of the Frontier Collaborative Research Center and a Research Planning Officer of the Strategic Research Planning Office in the instutute. Prior to joining the Tokyo Institute of Technology in 1999, Dr. Iwai held several research positions with Toshiba Corporation. Dr. Iwai has developed several generations of high density static RAM's, dynamic RAM's and logic LSI's including CMOS, bipolar, and Bi-CMOS devices. His current research interests are downsizing of CMOS, high K gate insulator, ultra-shallow junction, and RF silicon technologies for mobile telecommunication. Dr. Iwai has been awarded 36 patents since 1980 and has authored or coauthored over 200 papers. He is a fellow of IEEE and is currently Vice President of the Electron Devices Society.

Place:
Siegel Hall
Illinois Institute of Technology
Chicago, Illinois