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PAST
MEETING
Wednesday,
September 21st, 2005
3D: DESIGN TO VOLUME
A LOOK AT VARIOUS 3D APPLICATIONS, THEIR DESIGNS, AND ULTIMATE SILICON
RESULTS
PRESENTATION FILE 1 of 5 (2.9 MB)
PRESENTATION
FILE 1 of 5 (5.8 MB)
PRESENTATION
FILE 1 of 5 (8.7 MB)
PRESENTATION
FILE 1 of 5 (8.9 MB)
PRESENTATION
FILE 1 of 5 (1.5 MB)
Presented
by: Robert
Patti, Tezzaron Semiconductor
Presented Jointly with:
The Electron Devices Society Distinguished Lecturer Program
Robert Patti of Tezzaron Semiconductor discussed various types
of 3D IC integration, issues, and Tezzaron's solutions. The Tezzaron
process for wafer scale 3D assembly was covered and a small 3D processor/
memory device was demonstrated.
Robert Patti, 42, is the founder and CTO of Tezzaron Semiconductor
Corporation, where he provides system design and guidance to other
members of the Tezzaron staff.
Mr. Patti graduated from Rose-Hulman Institute of Technology with
BSEE/CS and BSPH degrees in 1985. His under-graduate work focused
on device physics, optics, and computer design. He also received
a minor in Russian.
As a member of IEEE, Mr. Patti has presented topics at a number
of conferences.
Place:
Motorola
Schaumburg, Illinois
Attendance:
Members:
Guests:
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