|
 |
|
|
Technical
Seminar |
|
|
|
|
|
Technology
Impacts from the New Wave of Architectures for Media-Rich Workloads |
|
|
DATE/TIME
Friday, August 26, 2011 (11:30am to 12:45pm)
NOTE NEW TIME!!! |
|
PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
|
|
DIRECTIONS
|
|
From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 11:15am for security sign-in and escort.
|
|
COST
Free. As always, food &
drinks will be provided. |
|
RSVP
Send e-mail to
https://gomartin.net/sscs/2011/rsvp_2011_08_26.htm |
|
|
ABSTRACT |
|
This presentation is an encore of an invited
plenary talk recently delivered at the 2011 Symposia on VLSI Technology
and Circuits in Kyoto, Japan. |
|
As the growth in rich and multi-media
workloads begin to dominate the compute cycles of our next-generation
processors, a revolution in architecture is taking place to efficiently
deal with them. This revolution involves the synergistic
combination of parallel and serial computation elements on-die. This
co-location makes for a rapidly evolving set of technology challenges.
With power limits front and center, the need for efficient, dense logic
with high-bandwidth interconnect makes the computing industry more
dependent than ever on continuing VLSI technology improvements. This
talk will explore these trends and the implications for next-generation
process development. |
|
PRESENTATION SLIDES
pdf (IEEE copyright) |
|
|
REFERENCE (IEEE copyright) |
|
|
|
|
SAM
NAFFZIGER (AMD, Fort Collins, CO)
|
 |
Sam
Naffziger received the BSEE degree from the California Institute of
Technology, Pasadena, CA, in 1988, and the MSEE degree from Stanford
University, Stanford, CA, in 1993. He has over 22 years experience in
microprocessor design, having led the implementation of PA-RISC, Itanium
and AMD processors working for Hewlett Packard, Intel and AMD. He
joined AMD in 2006, helping start the Mile High Design Center in Fort
Collins, CO where he has been responsible for power and frequency
optimization of mainstream processors and is the power efficiency
architect for AMD’s products. He holds 96 U.S. patents on processor
circuits and architecture and has over 25 IEEE publications and
presentations. Mr. Naffziger chaired the Digital subcommittee of the
International Solid-State Circuits Conference for 5 years, was Associate
Editor for the JSSC, and is a Corporate Fellow at AMD. |
|
|
|
|
|
|
|
