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Technical
Seminar |
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A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium®
Processor for Mission-Critical Servers |
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DATE/TIME
Friday, October 14, 2011 (10:00am to 11:15am) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 9:45am for security sign-in and escort.
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to
https://gomartin.net/sscs/2011/rsvp_2011_10_14.htm |
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ABSTRACT |
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This presentation is an extended encore of a
contributed paper delivered at the 2011 International Solid-State
Circuits Conference in San Francisco, CA |
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The next generation in the Intel® Itanium®
processor family, code named Poulson, has eight multi-threaded 64 bit
cores. Poulson is socket compatible with the current Intel® Itanium®
Processor 9300 series (Tukwila). The new design integrates a ring-based
system interface derived from portions of previous Xeon® and Itanium®
processors, and includes 32MB of Last Level Cache (LLC). The processor
is designed in Intel®’s 32nm CMOS technology utilizing high-K dielectric
metal gate transistors combined with nine layers of copper interconnect.
The 18.2×29.9mm2 die contains 3.1 billion transistors, with 720 million
allocated to the eight cores (Fig. 4.8.1). A total of 54MB of on die
cache is distributed throughout the core and system interface. Poulson
implements twice as many cores as Tukwila while lowering the thermal
design power (TDP) by 15W to 170W and increases the top frequency of the
I/O and memory interfaces by 50% to 6.4GT/s. |
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PRESENTATION SLIDES
pdf (IEEE copyright) |
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REID
RIEDLINGER (Intel, Fort Collins, CO)
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Reid Riedlinger
received his MSEE from Montana State University in 1993. He then joined
Hewlett-Packard and worked on various PA-RISC and IPF processors. In
2004, Reid joined Intel Corporation as a Principal Engineer leading the
post silicon debug of Montecito, a dual core IPF processor. On Poulson, he
was the project lead for the development of the core as well as circuit
methodology and is currently responsible for leading the definition of
Intel’s future generation of Itanium processors. He holds 18 US patents
and has been an author on several internal and external conference
papers. |
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