Presentation by Dr. Dale Nelson: April 21, 2021

Tutorial on Algorithmic Analog to Digital Converters

In this talk, Dr. Nelson will show the basic concept behind algorithmic converters and why most use two comparators for a “1.5 bits per stage” versus single bit per stage design. Effects of errors in gain, addition/subtraction, and comparison are discussed and simulated using a spread-sheet formulation and also a simulation using Python. A circuit implementation based on a student’s thesis is also shown and discussed.

Dale Nelson received his BSEE degree from the University of Nebraska, and joined Indianapolis Bell Laboratories in 1967. Through Bell Labs programs, he received his MSEE and Ph.D. EE degrees. He worked on various telephony projects, including using integrated circuits to improve the reliability and reduce the moving mechanical content of telephones. In 1984, he transferred to the Reading Laboratory. He was lead designer on a demonstration chip for basic ISDN which did 192 kilobits over standard twisted pair telephone lines. It required echo cancelling techniques using switched capacitor circuits, internal automatic gain adjustment, included a 16 bit by 32 word static dual port RAM and a 14 bit multi-stage switched capacitor digital to analog converter, increment/decrement NOR plane, plus a scrambler-descrambler, and the crystal oscillator that provided the main clock for the chip-set used at each end of the telephone line. Bipolar work involved creating a line-feed circuit using the CBIC-S 90V technology.

Later work had Dr. Nelson leading a team design circuits to support Static RAM memory for answering machines use instead of magnetic tape. This work involved an interface to the DSP that did the voice coding, and included amplifiers, A to D converters for converting voice and other analog quantities to digital, and D to A for voice playback.

He became manager of the group doing the analog portion of a special purpose DSP designed to directly support digital answering machine technology. This part was in 0.9um CMOS and included a 16 bit resistive string DAC. Dr. Nelson did the design of the successive approximation Analog to Digital converter which included a switch-capacitor comparator as a key component.

In 1999, Dr. Nelson took over as manager of a PLL group and led that group until he retired from Agere. Although his group was primarily responsible for PLLs, they did some converters as well, and were responsible for the ASIC crystal oscillator cells.

Dr. Nelson was also an Adjunct Professor at the University of Pennsylvania, has more that 28 patents, and is an author of two public technical papers.