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Technical
Seminar |
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Loopback Architecture for Wafer-Level At-Speed
Testing of Embedded HyperTransport
Processor Links |
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DATE/TIME
Thursday, October 15, 2009 (4:30pm to 6:00pm) |
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PLACE
AMD Fort Collins Campus (Fort
Collins, CO)
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DIRECTIONS
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From I-25, take Harmony Road Exit (Exit 265) westbound, and enter AMD
campus on right immediately following Harmony/Ziegler intersection.
AMD is located on the NW corner of Harmony Road and Ziegler Road.
Proceed to 3rd floor for escort to seminar auditorium. Non-AMD
employees: please arrive at 4:15pm for security sign-in and escort. |
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COST
Free. As always, food &
drinks will be provided. |
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RSVP
Send e-mail to Tin Tin Wee at
tintin.wee@amd.com. |
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ABSTRACT |
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This
paper is an extended encore of a paper recently presented at
Custom Integrated Circuits Conference
(CICC) 2009. We present transceiver serial loopback that
enables cost-effective wafer-level at-speed testing of HyperTransport
(HT) I/O for processor die-to-die communication. Besides facilitating
known-good-die testing, this feature provides observability of
multi-chip module (MCM) die-to-die links that are completely embedded
without external pin visibility. We demonstrate production screening of
45-nm SOI-CMOS wafers at 6.4 Gb/s. |
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PRESENTATION SLIDES
pdf |
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REFERENCE |
- A. Loke, B. Doyle, M. Oshima, W.
Williams, R. Lewis, C. Wang, A. Hanpachern, K. Tucker, P. Gurunath, G.
Asada, C. Lackey, T. T. Wee, and E. Fang, "Loopback
Architecture for Wafer-Level At-Speed Testing of Embedded HyperTransport
Processor Links," Proc. IEEE Custom Integrated Circuits Conf.,
pp. 605-608, Sep.
2009. (copyright by
IEEE)
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BRUCE DOYLE (AMD, Fort Collins, CO)
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Bruce Doyle
(M84) received the BSEE degree from Carleton University, Ottawa,
Canada in 1984. Since 1984, he has been involved in the design of
memories, graphics processors, analog circuits, mixed-signal ICs, and
high-performance microprocessors. From 2002 to 2006, he worked for
Hewlett-Packard / Intel in Fort Collins, CO, on the Itanium family of
high-performance microprocessors as a physical designer in high-speed
I/Os, clocking, and thermal systems. Currently, he is a Principal
Member of Technical Staff at Advanced Micro Devices in the Mile HIgh
Design Center, Fort Collins, CO, where he manages circuit development
for next-generation HyperTransport physical layers. His expertise
includes high-speed circuit design, analog circuit design, and
mixed-signal verification. He holds 11 US patents. |
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