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Officers - 2009


BRUCE DOYLE - Chair, IEEE Member
Bruce Doyle (M’84) received the B.S.E.E. degree from Carleton University, Ottawa, Canada in 1984.  Since 1984, he has been involved in the design of memories, graphics processors, analog circuits, mixed-signal IC’s, and high-performance microprocessors.  From 2002 to 2006, he worked for Hewlett-Packard / Intel in Fort Collins, CO, on the Itanium family of high-performance microprocessors as a physical designer in high-speed I/Os, clocking, and thermal systems.  Currently, he is a Principal Member of Technical Staff at Advanced Micro Devices in Fort Collins, CO, where he manages circuit development for next-generation HyperTransport physical layers.  His expertise includes high-speed circuit design, analog circuit design, and mixed-signal verification.  He holds 11 US patents.

ALVIN LOKE - Vice Chair, IEEE Senior Member

Alvin Loke (S'89-M'99-SM'04) received the B.A.Sc. (Eng. Physics) degree with highest honors from the University of British Columbia, Vancouver, Canada, in 1992, and the M.S.E.E. and Ph.D.E.E. degrees from Stanford University, Stanford, CA, in 1994 and 1999 respectively.  He was recipient of the Canadian NSERC 1967 Graduate Scholarship.  While at Stanford, his research focused on copper interconnects with low-K polymer dielectric.  He has interned at Texas Instruments, Motorola, and at Sumitomo Electric Industries (Osaka).  In 1998, he joined Hewlett-Packard Labs, Palo Alto, CA where he was involved in process integration of embedded ferroelectric memory.  In 1999, when Agilent Technologies divested from Hewlett-Packard, he was assigned to Chartered Semiconductor Manufacturing, Singapore, to work on copper and local interconnect integration.

In 2001, he transferred to Fort Collins, CO, where he designed CMOS phase-locked loop circuits for low-jitter embedded SerDes I/O and ASIC core clocking. In 2006, he joined Advanced Micro Devices in Fort Collins, CO, as Senior Member of Technical Staff, presently designing analog/mixed-signal circuits for HyperTransport links in 45nm and 32nm SOI CMOS.  Dr. Loke has authored over two dozen technical publications and holds 10 US patents.  He presently serves on the CICC technical program committee, SSCS Chapters committee, and is a technical reviewer for IEEE journals.  He is also an active member of the ECE Department Industrial Advisory Board at Colorado State University.

TIN TIN WEE - Webmaster, IEEE Senior Member

Tin Tin Wee (M'04-SM'05) received her B. Tech. (Electronics Eng.) from the National University of Singapore, Singapore, in 1999.  Prior to receiving her B. Tech., she was an Associate Engineer at International Video Products, Singapore, where she involved in RF test, measurement, and failure analysis of consumer video electronics.  In 1996, she joined Chartered Semiconductor Manufacturing, Singapore, as Process Integration Engineer where she was engaged in multiple aspects of 0.25um, 0.18um, and 0.15um technology development and transfer.  Activities included SRAM development, yield enhancement, and most recently, copper and local interconnect module integration.  Ms. Wee returned to the National University of Singapore to study circuits and systems, and completed her M.S.E.E. degree in 2001.  In 2004, she joined Agilent Technologies (now  Avago Technologies) where she was involved in bench test, characterization, and debug of

130nm and 90nm CMOS ASIC's with low-jitter embedded SerDes and core clocking PLL's.  In 2006, she joined Advanced Micro Devices in Fort Collins, CO, where she presently designs analog/mixed-signal circuits for HyperTransport links in 45nm and 32nm SOI CMOS.  She has authored three papers and holds three US patents.


BOB BARNES - Treasurer, IEEE Senior Member
Bob Barnes (S'77-M'81-SM'05) received his B.S.E.E. degree (summa cum laude) from Washington State University, Pullman, WA, in 1980, and the M.S.E.E. degree from Stanford University, Stanford, CA, in 1987.  Prior to his undergraduate studies, he served in the United States Air Force as an Electronics Technician repairing and maintaining ground-based navigation transmitters.  He joined Hewlett-Packard's Disk Memory Division, Boise, ID, in 1980 where he worked on disk drive head/servo characterization, and advanced read channel designs.  In 1996, he joined Hewlett-Packard's (now Avago Technologies') integrated circuits design center in Fort Collins, CO where he is currently a Senior Design Engineer developing 90nm and 65nm CMOS mixed-signal phase-locked loop architectures and circuits for low-jitter embedded SerDes I/O applications.  He holds eight US patents in areas of disk drive and IC design, and has authored two papers.

STEVE MARTIN - Secretary, IEEE Member

Steve Martin (S’99-M’05) received a B.S.E.E. with highest honors from the University of Florida, Gainesville, FL, in 1999 and M.S.E.E. and Ph.D.E.E. from the University of Michigan, Ann Arbor, MI, in 2002 and 2005, respectively.  He is a recipient of a NSF Graduate Research Fellowship.  His research focused on CMOS-integrated chemical sensors for trace environmental detection and low-power, low-noise analog and digital circuits.  Dr. Martin has held positions at Accuri Instruments where he developed a low-noise analog front end for a novel flow cytometer, at Sonetics Ultrasound where he designed analog integrated electronics for a CMUT array, and at Intel Corp. where he designed a 6Gb/s line driver in 65nm CMOS.  He is currently with Avago Technologies, Fort Collins, CO, where he is a research scientist developing acoustic technologies.  Dr. Martin has over a dozen technical publications, has served as a reviewer for several SBIR programs, and has co-authored a book chapter on CMOS-integrated chemical sensors.


VISVESH SATHE - Educational Activities, IEEE Member
Visvesh Sathe (S'02-M'07) received the B.Tech. degree in electrical engineering in 2001 from the Indian Institute of Technology, Bombay, India, and the M.S. and Ph.D. degrees in electrical engineering and computer science in 2004 and 2007 respectively from the University of Michigan, Ann Arbor.  While at Michigan, his research focused on low-energy circuit design with particular emphasis on resonant-clocked digital design.  He has held internship positions at the IBM T.J Watson Research Center and Cyclos Semiconductor, a start-up focusing on resonant-clocked microprocessors.  In 2007, he joined the power management group at Advanced Micro Devices, Fort Collins, CO, as a Senior Design Engineer exploring and implementing power reduction techniques for next-generation processors.  Dr. Sathe has authored 11 technical publications and two US patents.

Officers for Past Years