PPT Slide

A Compact Terabit-class ATM switching Fabric Using a 20-Gbit/s

subnetwork LSI and Free-space Optical Interconnections

S. Hino, K. Hirabayashi, T. Yamamoto, Y. Ohtomo*, and S. Yasuda*

NTT Optical Network Systems Laboratories

*NTT System Electronics Laboratories

Progress in our ATM-switching LSI chips

Process

CMOS,

0.8

m

m

(GLOBECOM'92)

Port speed

600 Mbit/s

CMOS,

0.5

m

m

(ISS'95)

2.5 Gbit/s

Number of ports

in a chip

2

X 2

2

X 2

CMOS/SIMOX

0.25

m

m

(ISSCC'97)

2.5 Gbit/s

Data throughput

between boards

8

X 8

4.8

Gbit/s

40

Gbit/s

320

Gbit/s

-

High-density, large-scale free-space optical interconnection

Key issues for constructing an "Over Tbit/s" switching system

-

Arrangement of the switching LSIs in MCMs/boards/cabinets

Number of ports

in a board

4

8

64

-

Large-scale, high-speed switching LSIs

Next slide

Back to first slide

View graphic version